[Vulkan] fix FBO path reading from output variables for alpha test
Makes FBO follow the same pattern as FSI by using function scoped intermediate variables
This commit is contained in:
Herman S.
@@ -472,13 +472,15 @@ void SpirvShaderTranslator::CompleteFragmentShaderInMain() {
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if ((color_targets_written & 0b1) && !IsExecutionModeEarlyFragmentTests()) {
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spv::Id fsi_sample_mask_in_rt_0_alpha_tests = spv::NoResult;
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spv::Block* block_fsi_rt_0_alpha_tests_rt_written_head = nullptr;
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spv::Block* block_fsi_rt_0_alpha_tests_rt_written_merge = nullptr;
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spv::Block* block_rt_0_alpha_tests_rt_written_head = nullptr;
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spv::Block* block_rt_0_alpha_tests_rt_written_merge = nullptr;
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builder_->makeNewBlock();
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if (edram_fragment_shader_interlock_) {
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if (var_main_fsi_color_written_ != spv::NoResult) {
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// Skip the alpha test and alpha to coverage if the render target 0 is not
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// written to dynamically.
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fsi_sample_mask_in_rt_0_alpha_tests = main_fsi_sample_mask_;
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// written to dynamically. This check is used by both FSI and FBO paths.
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if (edram_fragment_shader_interlock_) {
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fsi_sample_mask_in_rt_0_alpha_tests = main_fsi_sample_mask_;
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}
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spv::Id rt_0_written = builder_->createBinOp(
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spv::OpINotEqual, type_bool_,
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builder_->createBinOp(
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@@ -487,32 +489,30 @@ void SpirvShaderTranslator::CompleteFragmentShaderInMain() {
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spv::NoPrecision),
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builder_->makeUintConstant(0b1)),
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const_uint_0_);
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block_fsi_rt_0_alpha_tests_rt_written_head = builder_->getBuildPoint();
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spv::Block& block_fsi_rt_0_alpha_tests_rt_written =
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builder_->makeNewBlock();
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block_fsi_rt_0_alpha_tests_rt_written_merge = &builder_->makeNewBlock();
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builder_->createSelectionMerge(
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block_fsi_rt_0_alpha_tests_rt_written_merge,
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spv::SelectionControlDontFlattenMask);
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block_rt_0_alpha_tests_rt_written_head = builder_->getBuildPoint();
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spv::Block& block_rt_0_alpha_tests_rt_written = builder_->makeNewBlock();
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block_rt_0_alpha_tests_rt_written_merge = &builder_->makeNewBlock();
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builder_->createSelectionMerge(block_rt_0_alpha_tests_rt_written_merge,
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spv::SelectionControlDontFlattenMask);
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{
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std::unique_ptr<spv::Instruction> rt_0_written_branch_conditional_op =
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std::make_unique<spv::Instruction>(spv::OpBranchConditional);
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rt_0_written_branch_conditional_op->addIdOperand(rt_0_written);
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rt_0_written_branch_conditional_op->addIdOperand(
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block_fsi_rt_0_alpha_tests_rt_written.getId());
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block_rt_0_alpha_tests_rt_written.getId());
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rt_0_written_branch_conditional_op->addIdOperand(
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block_fsi_rt_0_alpha_tests_rt_written_merge->getId());
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block_rt_0_alpha_tests_rt_written_merge->getId());
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// More likely to write to the render target 0 than not.
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rt_0_written_branch_conditional_op->addImmediateOperand(2);
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rt_0_written_branch_conditional_op->addImmediateOperand(1);
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builder_->getBuildPoint()->addInstruction(
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std::move(rt_0_written_branch_conditional_op));
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}
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block_fsi_rt_0_alpha_tests_rt_written.addPredecessor(
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block_fsi_rt_0_alpha_tests_rt_written_head);
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block_fsi_rt_0_alpha_tests_rt_written_merge->addPredecessor(
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block_fsi_rt_0_alpha_tests_rt_written_head);
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builder_->setBuildPoint(&block_fsi_rt_0_alpha_tests_rt_written);
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block_rt_0_alpha_tests_rt_written.addPredecessor(
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block_rt_0_alpha_tests_rt_written_head);
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block_rt_0_alpha_tests_rt_written_merge->addPredecessor(
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block_rt_0_alpha_tests_rt_written_head);
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builder_->setBuildPoint(&block_rt_0_alpha_tests_rt_written);
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}
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// Alpha test.
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@@ -533,10 +533,9 @@ void SpirvShaderTranslator::CompleteFragmentShaderInMain() {
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id_vector_temp_.clear();
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id_vector_temp_.push_back(builder_->makeIntConstant(3));
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spv::Id alpha_test_alpha = builder_->createLoad(
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builder_->createAccessChain(
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edram_fragment_shader_interlock_ ? spv::StorageClassFunction
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: spv::StorageClassOutput,
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output_or_var_fragment_data_[0], id_vector_temp_),
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builder_->createAccessChain(spv::StorageClassFunction,
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output_or_var_fragment_data_[0],
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id_vector_temp_),
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spv::NoPrecision);
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id_vector_temp_.clear();
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id_vector_temp_.push_back(
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@@ -627,22 +626,23 @@ void SpirvShaderTranslator::CompleteFragmentShaderInMain() {
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// Alpha to coverage.
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FSI_AlphaToMask();
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if (edram_fragment_shader_interlock_) {
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// Close the render target 0 written check.
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builder_->createBranch(block_fsi_rt_0_alpha_tests_rt_written_merge);
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spv::Block& block_fsi_rt_0_alpha_tests_rt_written_end =
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if (block_rt_0_alpha_tests_rt_written_merge) {
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// Close the render target 0 written check (used by both FSI and FBO).
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builder_->createBranch(block_rt_0_alpha_tests_rt_written_merge);
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spv::Block& block_rt_0_alpha_tests_rt_written_end =
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*builder_->getBuildPoint();
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builder_->setBuildPoint(block_fsi_rt_0_alpha_tests_rt_written_merge);
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if (!features_.demote_to_helper_invocation) {
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builder_->setBuildPoint(block_rt_0_alpha_tests_rt_written_merge);
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if (edram_fragment_shader_interlock_ &&
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!features_.demote_to_helper_invocation) {
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// The tests might have modified the sample mask via
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// fsi_sample_mask_in_rt_0_alpha_tests.
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id_vector_temp_.clear();
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id_vector_temp_.push_back(fsi_sample_mask_in_rt_0_alpha_tests);
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id_vector_temp_.push_back(
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block_fsi_rt_0_alpha_tests_rt_written_end.getId());
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block_rt_0_alpha_tests_rt_written_end.getId());
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id_vector_temp_.push_back(main_fsi_sample_mask_);
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id_vector_temp_.push_back(
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block_fsi_rt_0_alpha_tests_rt_written_head->getId());
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block_rt_0_alpha_tests_rt_written_head->getId());
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main_fsi_sample_mask_ =
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builder_->createOp(spv::OpPhi, type_uint_, id_vector_temp_);
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}
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@@ -1297,6 +1297,23 @@ void SpirvShaderTranslator::CompleteFragmentShaderInMain() {
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}
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}
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if (!edram_fragment_shader_interlock_) {
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// FBO path: Copy from Function-scoped variables to Output variables.
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// This is done at the end after alpha test/coverage so we can read the
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// color values during those operations.
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uint32_t color_targets_to_copy = current_shader().writes_color_targets();
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uint32_t color_target_index;
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while (xe::bit_scan_forward(color_targets_to_copy, &color_target_index)) {
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color_targets_to_copy &= ~(UINT32_C(1) << color_target_index);
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spv::Id var_color = output_or_var_fragment_data_[color_target_index];
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spv::Id out_color = output_fragment_data_[color_target_index];
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if (var_color != spv::NoResult && out_color != spv::NoResult) {
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builder_->createStore(builder_->createLoad(var_color, spv::NoPrecision),
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out_color);
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}
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}
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}
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if (edram_fragment_shader_interlock_) {
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if (block_fsi_if_after_depth_stencil_merge) {
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builder_->createBranch(block_fsi_if_after_depth_stencil_merge);
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@@ -3808,10 +3825,9 @@ void SpirvShaderTranslator::FSI_AlphaToMask() {
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id_vector_temp_.clear();
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id_vector_temp_.push_back(builder_->makeIntConstant(3)); // W component
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spv::Id alpha = builder_->createLoad(
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builder_->createAccessChain(
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edram_fragment_shader_interlock_ ? spv::StorageClassFunction
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: spv::StorageClassOutput,
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output_or_var_fragment_data_[0], id_vector_temp_),
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builder_->createAccessChain(spv::StorageClassFunction,
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output_or_var_fragment_data_[0],
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id_vector_temp_),
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spv::NoPrecision);
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// Load MSAA sample count to determine which mode to use.
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