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Add separate VMX/fpu mxcsr

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Add support for constant operands for most fpu instructions
Remove constant folding for most fpu cpde
half float
This commit is contained in:
chss95cs@gmail.com
2022-07-31 08:56:36 -07:00
parent 3185b0ac9c
commit 968f656d96
18 changed files with 687 additions and 611 deletions
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9
src/xenia/cpu/ppc/ppc_emit_altivec.cc
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@@ -364,7 +364,16 @@ int InstrEmit_mfvscr(PPCHIRBuilder& f, const InstrData& i) {
int InstrEmit_mtvscr(PPCHIRBuilder& f, const InstrData& i) {
// is this the right format?
//todo: what mtvscr does with the unused bits is implementation defined, figure out what it does
Value* v = f.LoadVR(i.VX128_1.RB);
Value* has_njm_value = f.Extract(v, (uint8_t)3, INT32_TYPE);
f.SetNJM(f.IsTrue(f.And(has_njm_value, f.LoadConstantInt32(65536))));
f.StoreContext(offsetof(PPCContext, vscr_vec), v);
return 0;
}

5
src/xenia/cpu/ppc/ppc_emit_fpu.cc
View File

@@ -382,7 +382,6 @@ int InstrEmit_mtfsfx(PPCHIRBuilder& f, const InstrData& i) {
return 1;
} else {
assert_zero(i.XFL.W);
// Store under control of mask.
// Expand the mask from 8 bits -> 32 bits.
uint32_t mask = 0;
@@ -402,7 +401,7 @@ int InstrEmit_mtfsfx(PPCHIRBuilder& f, const InstrData& i) {
// Update the system rounding mode.
if (mask & 0x7) {
f.SetRoundingMode(v);
f.SetRoundingMode(f.And(v, f.LoadConstantInt32(7)));
}
}
if (i.XFL.Rc) {
@@ -425,7 +424,7 @@ int InstrEmit_mtfsfix(PPCHIRBuilder& f, const InstrData& i) {
// Update the system rounding mode.
if (mask & 0x7) {
f.SetRoundingMode(fpscr);
f.SetRoundingMode(f.And(fpscr, f.LoadConstantInt32(7)));
}
if (i.X.Rc) {