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Massively disgusting and incomplete shader translator.

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This commit is contained in:
Ben Vanik
2013-10-12 22:14:23 -07:00
parent 0ef278325f
commit 96a857e892
10 changed files with 1145 additions and 60 deletions
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8
src/xenia/gpu/xenos/ucode.h
View File

@@ -297,6 +297,14 @@ XEPACKEDSTRUCT(instr_cf_exec_t, {
uint32_t address_mode : 1; // instr_addr_mode_t
uint32_t opc : 4; // instr_cf_opc_t
});
bool is_cond_exec() const {
return (this->opc == COND_EXEC) ||
(this->opc == COND_EXEC_END) ||
(this->opc == COND_PRED_EXEC) ||
(this->opc == COND_PRED_EXEC_END) ||
(this->opc == COND_EXEC_PRED_CLEAN) ||
(this->opc == COND_EXEC_PRED_CLEAN_END);
}
});
XEPACKEDSTRUCT(instr_cf_loop_t, {

68
src/xenia/gpu/xenos/ucode_disassembler.cc
View File

@@ -255,44 +255,50 @@ int disasm_alu(
output->append(" %sALU:\t", sync ? "(S)" : " ");
output->append("%s", vector_instructions[alu->vector_opc].name);
if (alu->pred_select & 0x2) {
// seems to work similar to conditional execution in ARM instruction
// set, so let's use a similar syntax for now:
output->append((alu->pred_select & 0x1) ? "EQ" : "NE");
if (!alu->scalar_write_mask && !alu->vector_write_mask) {
output->append(" <nop>\n");
}
output->append("\t");
if (alu->vector_write_mask) {
output->append("%s", vector_instructions[alu->vector_opc].name);
print_dstreg(output,
alu->vector_dest, alu->vector_write_mask, alu->export_data);
output->append(" = ");
if (vector_instructions[alu->vector_opc].num_srcs == 3) {
if (alu->pred_select & 0x2) {
// seems to work similar to conditional execution in ARM instruction
// set, so let's use a similar syntax for now:
output->append((alu->pred_select & 0x1) ? "EQ" : "NE");
}
output->append("\t");
print_dstreg(output,
alu->vector_dest, alu->vector_write_mask, alu->export_data);
output->append(" = ");
if (vector_instructions[alu->vector_opc].num_srcs == 3) {
print_srcreg(output,
alu->src3_reg, alu->src3_sel, alu->src3_swiz,
alu->src3_reg_negate, alu->src3_reg_abs);
output->append(", ");
}
print_srcreg(output,
alu->src3_reg, alu->src3_sel, alu->src3_swiz,
alu->src3_reg_negate, alu->src3_reg_abs);
output->append(", ");
}
print_srcreg(output,
alu->src1_reg, alu->src1_sel, alu->src1_swiz,
alu->src1_reg_negate, alu->src1_reg_abs);
if (vector_instructions[alu->vector_opc].num_srcs > 1) {
output->append(", ");
print_srcreg(output,
alu->src2_reg, alu->src2_sel, alu->src2_swiz,
alu->src2_reg_negate, alu->src2_reg_abs);
}
alu->src1_reg, alu->src1_sel, alu->src1_swiz,
alu->src1_reg_negate, alu->src1_reg_abs);
if (vector_instructions[alu->vector_opc].num_srcs > 1) {
output->append(", ");
print_srcreg(output,
alu->src2_reg, alu->src2_sel, alu->src2_swiz,
alu->src2_reg_negate, alu->src2_reg_abs);
}
if (alu->vector_clamp) {
output->append(" CLAMP");
}
if (alu->vector_clamp) {
output->append(" CLAMP");
}
if (alu->export_data) {
print_export_comment(output, alu->vector_dest, type);
}
if (alu->export_data) {
print_export_comment(output, alu->vector_dest, type);
}
output->append("\n");
output->append("\n");
}
if (alu->scalar_write_mask || !alu->vector_write_mask) {
// 2nd optional scalar op:

6
src/xenia/gpu/xenos/xenos.h
View File

@@ -45,8 +45,10 @@ typedef enum {
// XE_GPU_REG_SQ_PROGRAM_CNTL
typedef union {
XEPACKEDSTRUCTANONYMOUS({
uint32_t vs_regs : 8;
uint32_t ps_regs : 8;
uint32_t vs_regs : 6;
uint32_t : 2;
uint32_t ps_regs : 6;
uint32_t : 2;
uint32_t vs_resource : 1;
uint32_t ps_resource : 1;
uint32_t param_gen : 1;