Fixing totally broken vpkd3d128 and adding new pack instructions.

src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.dis

@@ -59,3 +59,39 @@ Disassembly of section .text:
 0000000000100068 <test_vpkd3d128_d3dcolor_3_3>:
   100068:	18 83 1e d0 	vpkd3d128 v4,v3,0,2,2
   10006c:	4e 80 00 20 	blr
+
+0000000000100070 <test_vpkd3d128_short2_invalid_0>:
+  100070:	18 85 1e 10 	vpkd3d128 v4,v3,1,0,0
+  100074:	4e 80 00 20 	blr
+
+0000000000100078 <test_vpkd3d128_short2_invalid_1>:
+  100078:	18 85 1e 10 	vpkd3d128 v4,v3,1,0,0
+  10007c:	4e 80 00 20 	blr
+
+0000000000100080 <test_vpkd3d128_short2_0>:
+  100080:	18 85 1e 10 	vpkd3d128 v4,v3,1,0,0
+  100084:	4e 80 00 20 	blr
+
+0000000000100088 <test_vpkd3d128_short2_1>:
+  100088:	18 85 1e 10 	vpkd3d128 v4,v3,1,0,0
+  10008c:	4e 80 00 20 	blr
+
+0000000000100090 <test_vpkd3d128_short2_2>:
+  100090:	18 85 1e 10 	vpkd3d128 v4,v3,1,0,0
+  100094:	4e 80 00 20 	blr
+
+0000000000100098 <test_vpkd3d128_float16_2_invalid_0>:
+  100098:	18 8d 1e 10 	vpkd3d128 v4,v3,3,0,0
+  10009c:	4e 80 00 20 	blr
+
+00000000001000a0 <test_vpkd3d128_float16_2_0>:
+  1000a0:	18 8d 1e 10 	vpkd3d128 v4,v3,3,0,0
+  1000a4:	4e 80 00 20 	blr
+
+00000000001000a8 <test_vpkd3d128_float16_4_invalid_0>:
+  1000a8:	18 96 1e 10 	vpkd3d128 v4,v3,1,2,0
+  1000ac:	4e 80 00 20 	blr
+
+00000000001000b0 <test_vpkd3d128_float16_4_0>:
+  1000b0:	18 96 1e 10 	vpkd3d128 v4,v3,1,2,0
+  1000b4:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.map

@@ -12,3 +12,12 @@
 0000000000000058 t test_vpkd3d128_d3dcolor_3_1
 0000000000000060 t test_vpkd3d128_d3dcolor_3_2
 0000000000000068 t test_vpkd3d128_d3dcolor_3_3
+0000000000000070 t test_vpkd3d128_short2_invalid_0
+0000000000000078 t test_vpkd3d128_short2_invalid_1
+0000000000000080 t test_vpkd3d128_short2_0
+0000000000000088 t test_vpkd3d128_short2_1
+0000000000000090 t test_vpkd3d128_short2_2
+0000000000000098 t test_vpkd3d128_float16_2_invalid_0
+00000000000000a0 t test_vpkd3d128_float16_2_0
+00000000000000a8 t test_vpkd3d128_float16_4_invalid_0
+00000000000000b0 t test_vpkd3d128_float16_4_0

src/alloy/frontend/ppc/test/bin/instr_vpkshss.dis

@@ -0,0 +1,13 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vpkshss.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vpkshss_0>:
+  100000:	10 a3 21 8e 	vpkshss v5,v3,v4
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vpkshss_1>:
+  100008:	10 a3 21 8e 	vpkshss v5,v3,v4
+  10000c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vpkshss.map

@@ -0,0 +1,2 @@
+0000000000000000 t test_vpkshss_0
+0000000000000008 t test_vpkshss_1

src/alloy/frontend/ppc/test/bin/instr_vpkswss.dis

@@ -0,0 +1,13 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vpkswss.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vpkswss_0>:
+  100000:	10 a3 21 ce 	vpkswss v5,v3,v4
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vpkswss_1>:
+  100008:	10 a3 21 ce 	vpkswss v5,v3,v4
+  10000c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vpkswss.map

@@ -0,0 +1,2 @@
+0000000000000000 t test_vpkswss_0
+0000000000000008 t test_vpkswss_1

src/alloy/frontend/ppc/test/instr_vpkd3d128.s

@@ -133,3 +133,82 @@ test_vpkd3d128_d3dcolor_3_3:
   blr
   #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
   #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]
+
+
+test_vpkd3d128_short2_invalid_0:
+  #_ REGISTER_IN v3 [43817E00, C37CFC00, 42A23EC8, 403DB757]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 1, 1, 0
+  .long 0x18851E10
+  blr
+  #_ REGISTER_OUT v3 [43817E00, C37CFC00, 42A23EC8, 403DB757]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
+test_vpkd3d128_short2_invalid_1:
+  #_ REGISTER_IN v3 [412FDF00, C09FBE00, 42A23EC8, 403DB757]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 1, 1, 0
+  .long 0x18851E10
+  blr
+  #_ REGISTER_OUT v3 [412FDF00, C09FBE00, 42A23EC8, 403DB757]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
+
+test_vpkd3d128_short2_0:
+  #_ REGISTER_IN v3 [40407FFF, 403F8001, 00000000, 00000000]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 1, 1, 0
+  .long 0x18851E10
+  blr
+  #_ REGISTER_OUT v3 [40407FFF, 403F8001, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
+test_vpkd3d128_short2_1:
+  #_ REGISTER_IN v3 [40404000, 403FC000, 40400003, 403F8001]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 1, 1, 0
+  .long 0x18851E10
+  blr
+  #_ REGISTER_OUT v3 [40404000, 403FC000, 40400003, 403F8001]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 4000C000]
+test_vpkd3d128_short2_2:
+  #_ REGISTER_IN v3 [4040FFFE, 403FF333, 42A23EC8, 403DB757]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 1, 1, 0
+  .long 0x18851E10
+  blr
+  #_ REGISTER_OUT v3 [4040FFFE, 403FF333, 42A23EC8, 403DB757]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFFF333]
+
+test_vpkd3d128_float16_2_invalid_0:
+  #_ REGISTER_IN v3 [3FC00000, BFC00000, 42A23EC8, 403DB757]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 3, 1, 0
+  .long 0x188D1E10
+  blr
+  #_ REGISTER_OUT v3 [3FC00000, BFC00000, 42A23EC8, 403DB757]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3E00BE00]
+
+test_vpkd3d128_float16_2_0:
+  #_ REGISTER_IN v3 [3F000000, BF000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 3, 1, 0
+  .long 0x188D1E10
+  blr
+  #_ REGISTER_OUT v3 [3F000000, BF000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3800B800]
+
+test_vpkd3d128_float16_4_invalid_0:
+  #_ REGISTER_IN v3 [3FC00000, BFC00000, 3FC00000, BFC00000]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 5, 2, 0
+  .long 0x18961E10
+  blr
+  #_ REGISTER_OUT v3 [3FC00000, BFC00000, 3FC00000, BFC00000]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 3E00BE00, 3E00BE00]
+
+test_vpkd3d128_float16_4_0:
+  #_ REGISTER_IN v3 [3F000000, BF000000, 3F000000, BF000000]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 5, 2, 0
+  .long 0x18961E10
+  blr
+  #_ REGISTER_OUT v3 [3F000000, BF000000, 3F000000, BF000000]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 3800B800, 3800B800]

src/alloy/frontend/ppc/test/instr_vpkshss.s

@@ -0,0 +1,17 @@
+test_vpkshss_0:
+  #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
+  vpkshss v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
+  #_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vpkshss_1:
+  #_ REGISTER_IN v3 [7FFF8000, 00020003, 00040005, 00060007]
+  #_ REGISTER_IN v4 [7FFF8000, 000A000B, 000C000D, 000E000F]
+  vpkshss v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFF8000, 00020003, 00040005, 00060007]
+  #_ REGISTER_OUT v4 [7FFF8000, 000A000B, 000C000D, 000E000F]
+  #_ REGISTER_OUT v5 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]

src/alloy/frontend/ppc/test/instr_vpkswss.s

@@ -0,0 +1,17 @@
+test_vpkswss_0:
+  #_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_IN v4 [00000005, 00000006, 00000007, 00000008]
+  vpkswss v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_OUT v4 [00000005, 00000006, 00000007, 00000008]
+  #_ REGISTER_OUT v5 [00010002, 00030004, 00050006, 00070008]
+
+test_vpkswss_1:
+  #_ REGISTER_IN v3 [7FFFFFFF, 80000000, 00000000, 00000004]
+  #_ REGISTER_IN v4 [7FFFFFFF, 80000000, 00000000, 00000008]
+  vpkswss v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFFFFFF, 80000000, 00000000, 00000004]
+  #_ REGISTER_OUT v4 [7FFFFFFF, 80000000, 00000000, 00000008]
+  #_ REGISTER_OUT v5 [7FFF8000, 00000004, 7FFF8000, 00000008]