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Constant tests for rldicr, rlwimi, rlwinm, rlwnm, sld, slw, srad, sradi, sraw, srawi, srd.

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gibbed
2015-05-13 03:14:06 -05:00
parent 5ebd4984ba
commit 96e549d301
11 changed files with 787 additions and 0 deletions
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99
src/xenia/cpu/frontend/test/instr_sraw.s
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@@ -9,6 +9,17 @@ test_sraw_1:
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_sraw_1_constant:
li r4, 1
li r5, 0
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_sraw_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
@@ -20,6 +31,17 @@ test_sraw_2:
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_sraw_2_constant:
li r4, -1
li r5, 0
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_sraw_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
@@ -31,6 +53,17 @@ test_sraw_3:
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_sraw_3_constant:
li r4, -1
li r5, 1
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_sraw_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 63
@@ -42,6 +75,17 @@ test_sraw_4:
#_ REGISTER_OUT r5 63
#_ REGISTER_OUT r6 1
test_sraw_4_constant:
li r4, -1
li r5, 63
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
#_ REGISTER_OUT r6 1
test_sraw_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 64
@@ -53,6 +97,17 @@ test_sraw_5:
#_ REGISTER_OUT r5 64
#_ REGISTER_OUT r6 0
test_sraw_5_constant:
li r4, -1
li r5, 64
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
#_ REGISTER_OUT r6 0
test_sraw_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 100
@@ -64,6 +119,17 @@ test_sraw_6:
#_ REGISTER_OUT r5 100
#_ REGISTER_OUT r6 1
test_sraw_6_constant:
li r4, -1
li r5, 100
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
#_ REGISTER_OUT r6 1
test_sraw_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 30
@@ -75,6 +141,17 @@ test_sraw_7:
#_ REGISTER_OUT r5 30
#_ REGISTER_OUT r6 1
test_sraw_7_constant:
li r4, -1
li r5, 30
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 30
#_ REGISTER_OUT r6 1
test_sraw_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 31
@@ -86,6 +163,17 @@ test_sraw_8:
#_ REGISTER_OUT r5 31
#_ REGISTER_OUT r6 1
test_sraw_8_constant:
li r4, -1
li r5, 31
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 31
#_ REGISTER_OUT r6 1
test_sraw_9:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 32
@@ -96,3 +184,14 @@ test_sraw_9:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 32
#_ REGISTER_OUT r6 1
test_sraw_9_constant:
li r4, -1
li r5, 32
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 32
#_ REGISTER_OUT r6 1