New ppc opcode decoder.

Seems to work and match up with the old decoder (which may be bad).
Old decoder remains until all functionality is replaced.

src/xenia/cpu/ppc/ppc_opcode.h

@@ -0,0 +1,479 @@
+// This code was autogenerated by tools/ppc-table-gen.py. Do not modify!
+// clang-format off
+#ifndef XENIA_CPU_PPC_PPC_OPCODE_H_
+#define XENIA_CPU_PPC_PPC_OPCODE_H_
+
+#include <cstdint>
+
+namespace xe {
+namespace cpu {
+namespace ppc {
+
+// All PPC opcodes in the same order they appear in ppc_instr_table.h:
+enum class PPCOpcode : uint32_t {
+  addcx,
+  addex,
+  addi,
+  addic,
+  addicx,
+  addis,
+  addmex,
+  addx,
+  addzex,
+  andcx,
+  andisx,
+  andix,
+  andx,
+  bcctrx,
+  bclrx,
+  bcx,
+  bx,
+  cmp,
+  cmpi,
+  cmpl,
+  cmpli,
+  cntlzdx,
+  cntlzwx,
+  crand,
+  crandc,
+  creqv,
+  crnand,
+  crnor,
+  cror,
+  crorc,
+  crxor,
+  dcba,
+  dcbf,
+  dcbi,
+  dcbst,
+  dcbt,
+  dcbtst,
+  dcbz,
+  dcbz128,
+  divdux,
+  divdx,
+  divwux,
+  divwx,
+  eciwx,
+  ecowx,
+  eieio,
+  eqvx,
+  extsbx,
+  extshx,
+  extswx,
+  fabsx,
+  faddsx,
+  faddx,
+  fcfidx,
+  fcmpo,
+  fcmpu,
+  fctidx,
+  fctidzx,
+  fctiwx,
+  fctiwzx,
+  fdivsx,
+  fdivx,
+  fmaddsx,
+  fmaddx,
+  fmrx,
+  fmsubsx,
+  fmsubx,
+  fmulsx,
+  fmulx,
+  fnabsx,
+  fnegx,
+  fnmaddsx,
+  fnmaddx,
+  fnmsubsx,
+  fnmsubx,
+  fresx,
+  frspx,
+  frsqrtex,
+  fselx,
+  fsqrtsx,
+  fsqrtx,
+  fsubsx,
+  fsubx,
+  icbi,
+  isync,
+  lbz,
+  lbzu,
+  lbzux,
+  lbzx,
+  ld,
+  ldarx,
+  ldbrx,
+  ldu,
+  ldux,
+  ldx,
+  lfd,
+  lfdu,
+  lfdux,
+  lfdx,
+  lfs,
+  lfsu,
+  lfsux,
+  lfsx,
+  lha,
+  lhau,
+  lhaux,
+  lhax,
+  lhbrx,
+  lhz,
+  lhzu,
+  lhzux,
+  lhzx,
+  lmw,
+  lswi,
+  lswx,
+  lvebx,
+  lvehx,
+  lvewx,
+  lvewx128,
+  lvlx,
+  lvlx128,
+  lvlxl,
+  lvlxl128,
+  lvrx,
+  lvrx128,
+  lvrxl,
+  lvrxl128,
+  lvsl,
+  lvsl128,
+  lvsr,
+  lvsr128,
+  lvx,
+  lvx128,
+  lvxl,
+  lvxl128,
+  lwa,
+  lwarx,
+  lwaux,
+  lwax,
+  lwbrx,
+  lwz,
+  lwzu,
+  lwzux,
+  lwzx,
+  mcrf,
+  mcrfs,
+  mcrxr,
+  mfcr,
+  mffsx,
+  mfmsr,
+  mfspr,
+  mftb,
+  mfvscr,
+  mtcrf,
+  mtfsb0x,
+  mtfsb1x,
+  mtfsfix,
+  mtfsfx,
+  mtmsr,
+  mtmsrd,
+  mtspr,
+  mtvscr,
+  mulhdux,
+  mulhdx,
+  mulhwux,
+  mulhwx,
+  mulldx,
+  mulli,
+  mullwx,
+  nandx,
+  negx,
+  norx,
+  orcx,
+  ori,
+  oris,
+  orx,
+  rldclx,
+  rldcrx,
+  rldiclx,
+  rldicrx,
+  rldicx,
+  rldimix,
+  rlwimix,
+  rlwinmx,
+  rlwnmx,
+  sc,
+  sldx,
+  slwx,
+  sradix,
+  sradx,
+  srawix,
+  srawx,
+  srdx,
+  srwx,
+  stb,
+  stbu,
+  stbux,
+  stbx,
+  std,
+  stdbrx,
+  stdcx,
+  stdu,
+  stdux,
+  stdx,
+  stfd,
+  stfdu,
+  stfdux,
+  stfdx,
+  stfiwx,
+  stfs,
+  stfsu,
+  stfsux,
+  stfsx,
+  sth,
+  sthbrx,
+  sthu,
+  sthux,
+  sthx,
+  stmw,
+  stswi,
+  stswx,
+  stvebx,
+  stvehx,
+  stvewx,
+  stvewx128,
+  stvlx,
+  stvlx128,
+  stvlxl,
+  stvlxl128,
+  stvrx,
+  stvrx128,
+  stvrxl,
+  stvrxl128,
+  stvx,
+  stvx128,
+  stvxl,
+  stvxl128,
+  stw,
+  stwbrx,
+  stwcx,
+  stwu,
+  stwux,
+  stwx,
+  subfcx,
+  subfex,
+  subficx,
+  subfmex,
+  subfx,
+  subfzex,
+  sync,
+  td,
+  tdi,
+  tw,
+  twi,
+  vaddcuw,
+  vaddfp,
+  vaddfp128,
+  vaddsbs,
+  vaddshs,
+  vaddsws,
+  vaddubm,
+  vaddubs,
+  vadduhm,
+  vadduhs,
+  vadduwm,
+  vadduws,
+  vand,
+  vand128,
+  vandc,
+  vandc128,
+  vavgsb,
+  vavgsh,
+  vavgsw,
+  vavgub,
+  vavguh,
+  vavguw,
+  vcfpsxws128,
+  vcfpuxws128,
+  vcfsx,
+  vcfux,
+  vcmpbfp,
+  vcmpbfp128,
+  vcmpeqfp,
+  vcmpeqfp128,
+  vcmpequb,
+  vcmpequh,
+  vcmpequw,
+  vcmpequw128,
+  vcmpgefp,
+  vcmpgefp128,
+  vcmpgtfp,
+  vcmpgtfp128,
+  vcmpgtsb,
+  vcmpgtsh,
+  vcmpgtsw,
+  vcmpgtub,
+  vcmpgtuh,
+  vcmpgtuw,
+  vcsxwfp128,
+  vctsxs,
+  vctuxs,
+  vcuxwfp128,
+  vexptefp,
+  vexptefp128,
+  vlogefp,
+  vlogefp128,
+  vmaddcfp128,
+  vmaddfp,
+  vmaddfp128,
+  vmaxfp,
+  vmaxfp128,
+  vmaxsb,
+  vmaxsh,
+  vmaxsw,
+  vmaxub,
+  vmaxuh,
+  vmaxuw,
+  vmhaddshs,
+  vmhraddshs,
+  vminfp,
+  vminfp128,
+  vminsb,
+  vminsh,
+  vminsw,
+  vminub,
+  vminuh,
+  vminuw,
+  vmladduhm,
+  vmrghb,
+  vmrghh,
+  vmrghw,
+  vmrghw128,
+  vmrglb,
+  vmrglh,
+  vmrglw,
+  vmrglw128,
+  vmsum3fp128,
+  vmsum4fp128,
+  vmsummbm,
+  vmsumshm,
+  vmsumshs,
+  vmsumubm,
+  vmsumuhm,
+  vmsumuhs,
+  vmulesb,
+  vmulesh,
+  vmuleub,
+  vmuleuh,
+  vmulfp128,
+  vmulosb,
+  vmulosh,
+  vmuloub,
+  vmulouh,
+  vnmsubfp,
+  vnmsubfp128,
+  vnor,
+  vnor128,
+  vor,
+  vor128,
+  vperm,
+  vperm128,
+  vpermwi128,
+  vpkd3d128,
+  vpkpx,
+  vpkshss,
+  vpkshss128,
+  vpkshus,
+  vpkshus128,
+  vpkswss,
+  vpkswss128,
+  vpkswus,
+  vpkswus128,
+  vpkuhum,
+  vpkuhum128,
+  vpkuhus,
+  vpkuhus128,
+  vpkuwum,
+  vpkuwum128,
+  vpkuwus,
+  vpkuwus128,
+  vrefp,
+  vrefp128,
+  vrfim,
+  vrfim128,
+  vrfin,
+  vrfin128,
+  vrfip,
+  vrfip128,
+  vrfiz,
+  vrfiz128,
+  vrlb,
+  vrlh,
+  vrlimi128,
+  vrlw,
+  vrlw128,
+  vrsqrtefp,
+  vrsqrtefp128,
+  vsel,
+  vsel128,
+  vsl,
+  vslb,
+  vsldoi,
+  vsldoi128,
+  vslh,
+  vslo,
+  vslo128,
+  vslw,
+  vslw128,
+  vspltb,
+  vsplth,
+  vspltisb,
+  vspltish,
+  vspltisw,
+  vspltisw128,
+  vspltw,
+  vspltw128,
+  vsr,
+  vsrab,
+  vsrah,
+  vsraw,
+  vsraw128,
+  vsrb,
+  vsrh,
+  vsro,
+  vsro128,
+  vsrw,
+  vsrw128,
+  vsubcuw,
+  vsubfp,
+  vsubfp128,
+  vsubsbs,
+  vsubshs,
+  vsubsws,
+  vsububm,
+  vsububs,
+  vsubuhm,
+  vsubuhs,
+  vsubuwm,
+  vsubuws,
+  vsum2sws,
+  vsum4sbs,
+  vsum4shs,
+  vsum4ubs,
+  vsumsws,
+  vupkd3d128,
+  vupkhpx,
+  vupkhsb,
+  vupkhsb128,
+  vupkhsh,
+  vupklpx,
+  vupklsb,
+  vupklsb128,
+  vupklsh,
+  vxor,
+  vxor128,
+  xori,
+  xoris,
+  xorx,
+  kInvalid,
+};
+
+}  // namespace ppc
+}  // namespace cpu
+}  // namespace xe
+
+#endif  // XENIA_CPU_PPC_PPC_OPCODE_H_