fabi/Xenia-Canary
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[Testing] Remove tests for unimplemented instructions

Browse Source
This commit is contained in:
Herman S.
2026-02-12 17:25:24 +09:00
parent c741b31378
commit 9b41d1d614
2 changed files with 0 additions and 364 deletions
Download Patch File Download Diff File Expand all files Collapse all files

182
src/xenia/cpu/ppc/testing/instr__gen_vupkhpx.s
View File

@@ -1,182 +0,0 @@
test_vupkhpx_1_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
test_vupkhpx_2_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00000000, 00000001, 00000000, 00000001]
test_vupkhpx_3_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00000000, FF1F1F1F, FF1F1F1F, 00000000]
test_vupkhpx_4_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000001, 00001003, 00010005, 00011007]
test_vupkhpx_5_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [0000000D, 0000000D, 0000000D, 0000000D]
test_vupkhpx_6_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00000011, 00081113, 00110215, 00191317]
test_vupkhpx_7_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [0000071F, FF1F1800, 00000000, FF1F1800]
test_vupkhpx_8_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00010004, 00010004, 00010004, 00010004]
test_vupkhpx_9_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00011807, 00011807, 00011807, 00011807]
test_vupkhpx_10_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00020008, 00020008, 00020008, 00020008]
test_vupkhpx_11_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00041012, 00041012, 00041012, 00041012]
test_vupkhpx_12_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00041114, 00151318, FF011B05, 00101901]
test_vupkhpx_13_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [000F1C00, 00000000, 000F1E00, 00000000]
test_vupkhpx_14_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00100900, 00000000, FF100900, 00000000]
test_vupkhpx_15_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [001F1C00, 00001003, 00010005, 00011007]
test_vupkhpx_16_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FF000008, 00040010, FF00040F, 00000000]
test_vupkhpx_17_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FF0F1C00, 00000000, FF0F1E00, 00000000]
test_vupkhpx_18_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FF100900, 00000000, 00100D00, 00000000]
test_vupkhpx_19_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FF130E0D, FF130E0D, FF130E0D, FF130E0D]
test_vupkhpx_20_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FF1E0719, FF1E171B, FF1F071D, FF1F171F]
test_vupkhpx_21_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FF1F171E, FF1F171E, FF1F171E, FF1F171E]
test_vupkhpx_22_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FF1F1F1C, FF1F1F1D, FF1F1F1E, FF1F1F1F]
test_vupkhpx_23_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FF1F1F1D, FF1F1B1E, 00000002, 00000401]
test_vupkhpx_24_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FF1F1F1F, 00000801, 001C0310, FF1F1F1F]
test_vupkhpx_25_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FF1F1F1F, FF1F1C00, 00000000, 0000031F]
test_vupkhpx_26_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vupkhpx v2, v1
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FF1F1F1F, FF1F1F1F, FF1F1F1F, FF1F1F1F]

182
src/xenia/cpu/ppc/testing/instr__gen_vupklpx.s
View File

@@ -1,182 +0,0 @@
test_vupklpx_1_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
test_vupklpx_2_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00000000, 00000001, 00000000, 00000001]
test_vupklpx_3_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00000000, 00000000, FF1F1F1F, 00000000]
test_vupklpx_4_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00020009, 0002100B, 0003000D, 0003100F]
test_vupklpx_5_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [0000000D, 0000000D, 0000000D, 0000000D]
test_vupklpx_6_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FF020419, FF0A151B, FF13061D, FF1B171F]
test_vupklpx_7_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FF1F1800, 0000071F, FF1F1F1F, 0000071F]
test_vupklpx_8_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00010004, 00010004, 00010004, 00010004]
test_vupklpx_9_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00011807, 00011807, 00011807, 00011807]
test_vupklpx_10_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00020008, 00020008, 00020008, 00020008]
test_vupklpx_11_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00041012, 00041012, 00041012, 00041012]
test_vupklpx_12_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00040902, 000C1A04, 00150B06, 001D1C08]
test_vupklpx_13_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [000F1C0C, FF13060D, 000F1F13, 000C1913]
test_vupklpx_14_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00100B10, 00000000, FF100B10, 00000000]
test_vupklpx_15_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [001F1C00, 0002100B, 0003000D, 0003100F]
test_vupklpx_16_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [001F1F1F, FF1F1F1F, FF031F1F, FF1F1F1F]
test_vupklpx_17_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FF0F1C0C, FF13060D, FF0F1F13, 000C1913]
test_vupklpx_18_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FF100D00, 00000000, 00100F10, 00000000]
test_vupklpx_19_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FF130E0D, FF130E0D, 00010001, 00001003]
test_vupklpx_20_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00000001, 00001003, 00010005, 00011007]
test_vupklpx_21_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FF1F171E, FF1F171E, FF1F171E, FF1F171E]
test_vupklpx_22_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00000000, 00000001, 00000002, 00000003]
test_vupklpx_23_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FF1F1F1C, FF1F1B1D, 00000003, 00000402]
test_vupklpx_24_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FF1F1F1F, FF1F1F1F, 00000000, 00000000]
test_vupklpx_25_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FF1F1F1E, FF1F1B1F, 00000001, 00000400]
test_vupklpx_26_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vupklpx v2, v1
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FF1F1F1F, FF1F1F1F, FF1F1F1F, FF1F1F1F]