diff --git a/src/xenia/cpu/backend/a64/a64_seq_vector.cc b/src/xenia/cpu/backend/a64/a64_seq_vector.cc index 9e32847fd..a02fe80b8 100644 --- a/src/xenia/cpu/backend/a64/a64_seq_vector.cc +++ b/src/xenia/cpu/backend/a64/a64_seq_vector.cc @@ -31,8 +31,7 @@ volatile int anchor_vector = 0; struct SPLAT_I8 : Sequence> { static void Emit(A64Emitter& e, const EmitArgType& i) { if (i.src1.is_constant) { - e.movi(VReg(i.dest.reg().getIdx()).b16, - static_cast(i.src1.constant())); + LoadV128Const(e, i.dest.reg().getIdx(), vec128b(i.src1.constant())); } else { e.dup(VReg(i.dest.reg().getIdx()).b16, i.src1); } @@ -41,8 +40,7 @@ struct SPLAT_I8 : Sequence> { struct SPLAT_I16 : Sequence> { static void Emit(A64Emitter& e, const EmitArgType& i) { if (i.src1.is_constant) { - e.mov(e.w0, static_cast(i.src1.constant() & 0xFFFF)); - e.dup(VReg(i.dest.reg().getIdx()).h8, e.w0); + LoadV128Const(e, i.dest.reg().getIdx(), vec128s(i.src1.constant())); } else { e.dup(VReg(i.dest.reg().getIdx()).h8, i.src1); } @@ -51,10 +49,7 @@ struct SPLAT_I16 : Sequence> { struct SPLAT_I32 : Sequence> { static void Emit(A64Emitter& e, const EmitArgType& i) { if (i.src1.is_constant) { - uint32_t val = static_cast(i.src1.constant()); - // Use movz/movn via mov(xreg, uint64) for full 32-bit range. - e.mov(e.x0, static_cast(val)); - e.dup(VReg(i.dest.reg().getIdx()).s4, e.w0); + LoadV128Const(e, i.dest.reg().getIdx(), vec128i(i.src1.constant())); } else { e.dup(VReg(i.dest.reg().getIdx()).s4, i.src1); } @@ -63,13 +58,8 @@ struct SPLAT_I32 : Sequence> { struct SPLAT_F32 : Sequence> { static void Emit(A64Emitter& e, const EmitArgType& i) { if (i.src1.is_constant) { - union { - float f; - uint32_t u; - } c; - c.f = i.src1.constant(); - e.mov(e.w0, static_cast(c.u)); - e.dup(VReg(i.dest.reg().getIdx()).s4, e.w0); + LoadV128Const(e, i.dest.reg().getIdx(), + vec128i(std::bit_cast(i.src1.constant()))); } else { int src_idx = i.src1.reg().getIdx(); e.dup(VReg(i.dest.reg().getIdx()).s4, VReg(src_idx).s4[0]);