[GPU] Cleanup definitions of some registers

VS/PS_NUM_REG is 6-bit on Adreno 200, and games aren't seen using the
bit 7 to indicate that no GPRs are used. It's not clear why Freedreno
configures it this way.

Some texture fetch fields were deprecated or moved during the development
of the Xenos, reflect that in the comments.

Add definitions of the registers configuring the conversion of vertex
positions to fixed-point. Although there isn't much that can be done with
it when emulating using PC GPU APIs, there are some places in Xenia that
wrongly (though sometimes deliberately, for results closer to the behavior
of the host GPU) assume that the conversion works like in Direct3D 10+,
however the Xenos supports only up to 4 subpixel bits rather than 8. The
effects of this difference are largely negligible, though.

Also add more detailed info about register references and differences from
other ATI/AMD GPUs for potential future contributors.

src/xenia/gpu/register_table.inc

@@ -2,7 +2,7 @@
  ******************************************************************************
  * Xenia : Xbox 360 Emulator Research Project                                 *
  ******************************************************************************
- * Copyright 2013 Ben Vanik. All rights reserved.                             *
+ * Copyright 2025 Ben Vanik. All rights reserved.                             *
  * Released under the BSD license - see LICENSE in the root for more details. *
  ******************************************************************************
  */
@@ -10,8 +10,25 @@
 // This is a partial file designed to be included by other files when
 // constructing various tables.
 
-// Almost all of these values are taken directly from:
-// https://github.com/freedreno/amd-gpu/blob/master/include/reg/yamato/22/yamato_offset.h
+// Most 3D registers are the same as in the Qualcomm Adreno 200 (AMD Z430,
+// another R400 architecture family chip):
+// https://github.com/UDOOboard/Kernel_Unico/blob/master/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h
+// https://github.com/freedreno/amd-gpu/blob/master/include/reg/yamato/10/yamato_offset.h
+//
+// The addresses in this file are specified in dwords, similarly to how they are
+// defined in yamato_offset.h. AMD, however, generally uses byte addresses in
+// their documentation and open source drivers, so when looking up similar
+// registers there, multiply by 4 and convert to hexadecimal.
+//
+// Display controller register addresses mostly match the M56 ones:
+// https://www.x.org/docs/AMD/old/RRG-216M56-03oOEM.pdf
+//
+// 3D registers on the later chips such as the R600 are very different, but some
+// of them are still partially or fully the same, and also share the address.
+// However, on the R600, the 3D register space (at 0x8000 bytes, or 0x2000
+// dwords, on the Xenos) is split into config registers (at 0x8000 bytes) and
+// context registers (at 0x28000 bytes), but the lower bits of the address may
+// still be the same.
 
 //#define XE_GPU_REGISTER(index, type, name)