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[GPU] Align texture extents in loading to host buffer texel size accessed by the shader

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This commit is contained in:
Triang3l
2022-06-29 23:38:06 +03:00
parent 243683d2e9
commit a11b070fee
4 changed files with 38 additions and 15 deletions
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23
src/xenia/gpu/d3d12/d3d12_texture_cache.cc
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@@ -1147,7 +1147,8 @@ bool D3D12TextureCache::ClampDrawResolutionScaleToMaxSupported(
}
bool D3D12TextureCache::EnsureScaledResolveMemoryCommitted(
uint32_t start_unscaled, uint32_t length_unscaled) {
uint32_t start_unscaled, uint32_t length_unscaled,
uint32_t length_scaled_alignment_log2) {
assert_true(IsDrawResolutionScaled());
if (length_unscaled == 0) {
@@ -1162,8 +1163,12 @@ bool D3D12TextureCache::EnsureScaledResolveMemoryCommitted(
uint32_t draw_resolution_scale_area =
draw_resolution_scale_x() * draw_resolution_scale_y();
uint64_t first_scaled = uint64_t(start_unscaled) * draw_resolution_scale_area;
uint64_t last_scaled = uint64_t(start_unscaled + (length_unscaled - 1)) *
draw_resolution_scale_area;
uint64_t length_scaled_alignment_bits =
(UINT64_C(1) << length_scaled_alignment_log2) - 1;
uint64_t last_scaled = (uint64_t(start_unscaled + (length_unscaled - 1)) *
draw_resolution_scale_area +
length_scaled_alignment_bits) &
~length_scaled_alignment_bits;
const ui::d3d12::D3D12Provider& provider =
command_processor_.GetD3D12Provider();
@@ -1273,7 +1278,8 @@ bool D3D12TextureCache::EnsureScaledResolveMemoryCommitted(
}
bool D3D12TextureCache::MakeScaledResolveRangeCurrent(
uint32_t start_unscaled, uint32_t length_unscaled) {
uint32_t start_unscaled, uint32_t length_unscaled,
uint32_t length_scaled_alignment_log2) {
assert_true(IsDrawResolutionScaled());
if (!length_unscaled || start_unscaled >= SharedMemory::kBufferSize ||
@@ -1286,8 +1292,12 @@ bool D3D12TextureCache::MakeScaledResolveRangeCurrent(
uint32_t draw_resolution_scale_area =
draw_resolution_scale_x() * draw_resolution_scale_y();
uint64_t start_scaled = uint64_t(start_unscaled) * draw_resolution_scale_area;
uint64_t length_scaled_alignment_bits =
(UINT64_C(1) << length_scaled_alignment_log2) - 1;
uint64_t length_scaled =
uint64_t(length_unscaled) * draw_resolution_scale_area;
(uint64_t(length_unscaled) * draw_resolution_scale_area +
length_scaled_alignment_bits) &
~length_scaled_alignment_bits;
uint64_t last_scaled = start_scaled + (length_scaled - 1);
// Get one or two buffers that can hold the whole range.
@@ -1855,7 +1865,8 @@ bool D3D12TextureCache::LoadTextureDataFromResidentMemoryImpl(Texture& texture,
if (texture_resolution_scaled && (is_base || !scaled_mips_source_set_up)) {
uint32_t guest_size_unscaled = is_base ? d3d12_texture.GetGuestBaseSize()
: d3d12_texture.GetGuestMipsSize();
if (!MakeScaledResolveRangeCurrent(guest_address, guest_size_unscaled)) {
if (!MakeScaledResolveRangeCurrent(guest_address, guest_size_unscaled,
load_shader_info.source_bpe_log2)) {
command_processor_.ReleaseScratchGPUBuffer(copy_buffer,
copy_buffer_state);
return false;

8
src/xenia/gpu/d3d12/d3d12_texture_cache.h
View File

@@ -130,14 +130,16 @@ class D3D12TextureCache final : public TextureCache {
uint32_t& scale_x, uint32_t& scale_y,
const ui::d3d12::D3D12Provider& provider);
// Ensures the tiles backing the range in the buffers are allocated.
bool EnsureScaledResolveMemoryCommitted(uint32_t start_unscaled,
uint32_t length_unscaled) override;
bool EnsureScaledResolveMemoryCommitted(
uint32_t start_unscaled, uint32_t length_unscaled,
uint32_t length_scaled_alignment_log2 = 0) override;
// Makes the specified range of up to 1-2 GB currently accessible on the GPU.
// One draw call can access only at most one range - the same memory is
// accessible through different buffers based on the range needed, so aliasing
// barriers are required.
bool MakeScaledResolveRangeCurrent(uint32_t start_unscaled,
uint32_t length_unscaled);
uint32_t length_unscaled,
uint32_t length_scaled_alignment_log2 = 0);
// These functions create a view of the range specified in the last successful
// MakeScaledResolveRangeCurrent call because that function must be called
// before this.