[DXBC] Inline depth/stencil test
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@@ -2265,21 +2265,6 @@ class DxbcShaderTranslator : public ShaderTranslator {
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void CompletePixelShader_WriteToROV();
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void CompletePixelShader();
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// Writes a function that does early (or both early and late, when not
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// separating) depth/stencil testing for one sample (ROV only).
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// Input:
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// - system_temps_subroutine_[0].x - depth converted to 24 bits in bits 0:23.
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// - system_temp_rov_params_.y - depth sample EDRAM address.
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// Output:
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// - system_temps_subroutine_[0].x - resulting packed depth/stencil.
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// - system_temps_subroutine_[0].y - test result, bit 0 if test FAILED (so
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// coverage can be updated with XOR), and if depth/stencil is early, also
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// bit 4 if the pixel shader still needs to be done to check for
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// kills/alphatest/AtoC before writing the new stencil.
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// Local temps:
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// - system_temps_subroutine_[0].zw.
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// - system_temps_subroutine_[1].xy.
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void CompleteShaderCode_ROV_DepthStencilSampleSubroutine();
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void CompleteShaderCode();
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// Writes the original instruction disassembly in the output DXBC if enabled,
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@@ -2505,22 +2490,12 @@ class DxbcShaderTranslator : public ShaderTranslator {
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// Whether the faceness has been used in the pixel shader.
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bool in_front_face_used_;
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// Subroutine labels. D3D10_SB_OPCODE_LABEL is not counted as an instruction
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// in STAT.
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uint32_t label_rov_depth_stencil_sample_;
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// Number of currently allocated Xenia internal r# registers.
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uint32_t system_temp_count_current_;
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// Total maximum number of temporary registers ever used during this
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// translation (for the declaration).
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uint32_t system_temp_count_max_;
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// Registers for the needed count of non-main-subroutine-local variables.
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// This includes arguments.
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uint32_t system_temps_subroutine_;
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// Number of registers allocated for subroutines other than main.
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uint32_t system_temps_subroutine_count_;
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// Position in vertex shaders (because viewport and W transformations can be
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// applied in the end of the shader).
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uint32_t system_temp_position_;
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