[CPU] Detect FPSCR exceptions in UpdateFPSCR for Rc=1 FPU instructions

Implement SNaN detection and FPSCR exception tracking so that Rc=1 FPU
instructions (fadds., fmadds., etc.) correctly update CR1 with FPSCR
exception summary bits (FX, FEX, VX, OX). Previously these were
hardcoded to zero. Enable ~2k tests that were previously disabled.

src/xenia/cpu/ppc/ppc_hir_builder.h

@@ -59,7 +59,8 @@ class PPCHIRBuilder : public hir::HIRBuilder {
   void UpdateCR6(Value* src_value);
   Value* LoadFPSCR();
   void StoreFPSCR(Value* value);
-  void UpdateFPSCR(Value* result, bool update_cr1);
+  void UpdateFPSCR(Value* result, bool update_cr1, Value* src1 = nullptr,
+                   Value* src2 = nullptr, Value* src3 = nullptr);
   void CopyFPSCRToCR1();
   Value* LoadXER();
   void StoreXER(Value* value);