[CPU] Detect FPSCR exceptions in UpdateFPSCR for Rc=1 FPU instructions

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Implement SNaN detection and FPSCR exception tracking so that Rc=1 FPU
instructions (fadds., fmadds., etc.) correctly update CR1 with FPSCR
exception summary bits (FX, FEX, VX, OX). Previously these were
hardcoded to zero. Enable ~2k tests that were previously disabled.

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Herman S.

2026-02-15 00:50:56 +09:00

parent 0202be1af1

commit a769d70761

4 changed files with 151 additions and 2136 deletions

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src/xenia/cpu/ppc/testing/skip.txt

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