fabi/Xenia-Canary
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

More style.

Browse Source
This commit is contained in:
Ben Vanik
2015-08-07 21:29:03 -07:00
parent 14beb27ebc
commit a92566dfc5
131 changed files with 1141 additions and 1056 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/xenia/cpu/backend/x64/x64_sequences.cc
View File

@@ -24,6 +24,7 @@
#include "xenia/cpu/backend/x64/x64_sequences.h"
#include <algorithm>
#include <cstring>
#include <unordered_map>
@@ -47,8 +48,10 @@ namespace x64 {
using namespace Xbyak;
// TODO(benvanik): direct usings.
using namespace xe::cpu::hir;
using namespace xe::cpu;
using namespace xe::cpu::hir;
using xe::cpu::hir::Instr;
typedef bool (*SequenceSelectFn)(X64Emitter&, const Instr*);
std::unordered_map<uint32_t, SequenceSelectFn> sequence_table;
@@ -653,7 +656,7 @@ template <typename T, typename Tn, typename... Ts>
void Register() {
Register<T>();
Register<Tn, Ts...>();
};
}
#define EMITTER_OPCODE_TABLE(name, ...) \
void Register_##name() { Register<__VA_ARGS__>(); }
@@ -5447,8 +5450,8 @@ struct VECTOR_SHR_V128
}
}
// We've reached here if we don't have AVX2 and it's a variable shift
// TODO: native version
// We've reached here if we don't have AVX2 and it's a variable shift.
// TODO(benvanik): native version.
if (i.src2.is_constant) {
e.LoadConstantXmm(e.xmm0, i.src2.constant());
e.lea(e.r9, e.StashXmm(1, e.xmm0));
@@ -5535,8 +5538,7 @@ struct VECTOR_SHA_V128
}
e.vpsravd(i.dest, i.src1, e.xmm0);
} else {
// Emulated for now...
// TODO: Native version
// TODO(benvanik): native version.
if (i.src2.is_constant) {
e.LoadConstantXmm(e.xmm0, i.src2.constant());
e.lea(e.r9, e.StashXmm(1, e.xmm0));
@@ -5684,7 +5686,7 @@ struct VECTOR_ROTATE_LEFT_V128
// Merge:
e.vpor(i.dest, e.xmm1);
} else {
// TODO: Non-AVX2 native version
// TODO(benvanik): non-AVX2 native version.
e.lea(e.r8, e.StashXmm(0, i.src1));
e.lea(e.r9, e.StashXmm(1, i.src2));
e.CallNativeSafe(reinterpret_cast<void*>(EmulateVectorRotateLeftI32));

1
src/xenia/cpu/compiler/passes/context_promotion_pass.h
View File

@@ -11,6 +11,7 @@
#define XENIA_CPU_COMPILER_PASSES_CONTEXT_PROMOTION_PASS_H_
#include <cmath>
#include <vector>
#include "xenia/base/platform.h"
#include "xenia/cpu/compiler/compiler_pass.h"

4
src/xenia/cpu/compiler/passes/data_flow_analysis_pass.cc
View File

@@ -71,8 +71,8 @@ void DataFlowAnalysisPass::AnalyzeFlow(HIRBuilder* builder,
// Stash for value map. We may want to maintain this during building.
auto arena = builder->arena();
Value** value_map =
(Value**)arena->Alloc(sizeof(Value*) * max_value_estimate);
auto value_map = reinterpret_cast<Value**>(
arena->Alloc(sizeof(Value*) * max_value_estimate));
// Allocate incoming bitvectors for use by blocks. We don't need outgoing
// because they are only used during the block iteration.

2
src/xenia/cpu/compiler/passes/finalization_pass.cc
View File

@@ -44,7 +44,7 @@ bool FinalizationPass::Run(HIRBuilder* builder) {
while (label) {
if (!label->name) {
const size_t label_len = 6 + 4 + 1;
char* name = (char*)arena->Alloc(label_len);
char* name = reinterpret_cast<char*>(arena->Alloc(label_len));
snprintf(name, label_len, "_label%d", label->id);
label->name = name;
}

3
src/xenia/cpu/compiler/passes/register_allocation_pass.cc
View File

@@ -180,7 +180,8 @@ void RegisterAllocationPass::DumpUsage(const char* name) {
auto usage_set = usage_sets_.all_sets[i];
if (usage_set) {
fprintf(stdout, "set %s:\n", usage_set->set->name);
fprintf(stdout, " avail: %s\n", usage_set->availability.to_string().c_str());
fprintf(stdout, " avail: %s\n",
usage_set->availability.to_string().c_str());
fprintf(stdout, " upcoming uses:\n");
for (auto it = usage_set->upcoming_uses.begin();
it != usage_set->upcoming_uses.end(); ++it) {

3
src/xenia/cpu/compiler/passes/register_allocation_pass.h
View File

@@ -12,6 +12,7 @@
#include <algorithm>
#include <bitset>
#include <functional>
#include <vector>
#include "xenia/cpu/backend/machine_info.h"
@@ -24,7 +25,7 @@ namespace passes {
class RegisterAllocationPass : public CompilerPass {
public:
RegisterAllocationPass(const backend::MachineInfo* machine_info);
explicit RegisterAllocationPass(const backend::MachineInfo* machine_info);
~RegisterAllocationPass() override;
bool Run(hir::HIRBuilder* builder) override;

2
src/xenia/cpu/compiler/passes/validation_pass.cc
View File

@@ -37,7 +37,7 @@ bool ValidationPass::Run(HIRBuilder* builder) {
#if 0
StringBuffer str;
builder->Dump(&str);
printf(str.GetString());
printf("%s", str.GetString());
fflush(stdout);
str.Reset();
#endif // 0

8
src/xenia/cpu/compiler/passes/value_reduction_pass.cc
View File

@@ -79,10 +79,10 @@ bool ValueReductionPass::Run(HIRBuilder* builder) {
instr = block->instr_head;
while (instr) {
const OpcodeInfo* info = instr->opcode;
OpcodeSignatureType dest_type = GET_OPCODE_SIG_TYPE_DEST(info->signature);
OpcodeSignatureType src1_type = GET_OPCODE_SIG_TYPE_SRC1(info->signature);
OpcodeSignatureType src2_type = GET_OPCODE_SIG_TYPE_SRC2(info->signature);
OpcodeSignatureType src3_type = GET_OPCODE_SIG_TYPE_SRC3(info->signature);
auto dest_type = GET_OPCODE_SIG_TYPE_DEST(info->signature);
auto src1_type = GET_OPCODE_SIG_TYPE_SRC1(info->signature);
auto src2_type = GET_OPCODE_SIG_TYPE_SRC2(info->signature);
auto src3_type = GET_OPCODE_SIG_TYPE_SRC3(info->signature);
if (src1_type == OPCODE_SIG_TYPE_V) {
auto v = instr->src1.value;
if (!v->last_use) {

6
src/xenia/cpu/frontend/context_info.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_FRONTEND_CONTEXT_INFO_H_
#define XENIA_FRONTEND_CONTEXT_INFO_H_
#ifndef XENIA_CPU_FRONTEND_CONTEXT_INFO_H_
#define XENIA_CPU_FRONTEND_CONTEXT_INFO_H_
#include <cstddef>
#include <cstdint>
@@ -38,4 +38,4 @@ class ContextInfo {
} // namespace cpu
} // namespace xe
#endif // XENIA_FRONTEND_CONTEXT_INFO_H_
#endif // XENIA_CPU_FRONTEND_CONTEXT_INFO_H_

6
src/xenia/cpu/frontend/ppc_context.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_FRONTEND_PPC_CONTEXT_H_
#define XENIA_FRONTEND_PPC_CONTEXT_H_
#ifndef XENIA_CPU_FRONTEND_PPC_CONTEXT_H_
#define XENIA_CPU_FRONTEND_PPC_CONTEXT_H_
#include <cstdint>
@@ -229,4 +229,4 @@ static_assert(sizeof(PPCContext) % 64 == 0, "64b padded");
} // namespace cpu
} // namespace xe
#endif // XENIA_FRONTEND_PPC_CONTEXT_H_
#endif // XENIA_CPU_FRONTEND_PPC_CONTEXT_H_

530
src/xenia/cpu/frontend/ppc_disasm.cc
View File

@@ -17,117 +17,121 @@ namespace xe {
namespace cpu {
namespace frontend {
void Disasm_0(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s ???", i.type->name);
void Disasm_0(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s ???", i->type->name);
}
void Disasm__(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s", i.type->name);
void Disasm__(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s", i->type->name);
}
void Disasm_X_FRT_FRB(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s f%d, f%d", i.X.Rc ? -7 : -8, i.type->name,
i.X.Rc ? "." : "", i.X.RT, i.X.RB);
void Disasm_X_FRT_FRB(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s f%d, f%d", i->X.Rc ? -7 : -8, i->type->name,
i->X.Rc ? "." : "", i->X.RT, i->X.RB);
}
void Disasm_A_FRT_FRB(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s f%d, f%d", i.A.Rc ? -7 : -8, i.type->name,
i.A.Rc ? "." : "", i.A.FRT, i.A.FRB);
void Disasm_A_FRT_FRB(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s f%d, f%d", i->A.Rc ? -7 : -8, i->type->name,
i->A.Rc ? "." : "", i->A.FRT, i->A.FRB);
}
void Disasm_A_FRT_FRA_FRB(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s f%d, f%d, f%d", i.A.Rc ? -7 : -8, i.type->name,
i.A.Rc ? "." : "", i.A.FRT, i.A.FRA, i.A.FRB);
void Disasm_A_FRT_FRA_FRB(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s f%d, f%d, f%d", i->A.Rc ? -7 : -8, i->type->name,
i->A.Rc ? "." : "", i->A.FRT, i->A.FRA, i->A.FRB);
}
void Disasm_A_FRT_FRA_FRB_FRC(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s f%d, f%d, f%d, f%d", i.A.Rc ? -7 : -8, i.type->name,
i.A.Rc ? "." : "", i.A.FRT, i.A.FRA, i.A.FRB, i.A.FRC);
void Disasm_A_FRT_FRA_FRB_FRC(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s f%d, f%d, f%d, f%d", i->A.Rc ? -7 : -8,
i->type->name, i->A.Rc ? "." : "", i->A.FRT, i->A.FRA,
i->A.FRB, i->A.FRC);
}
void Disasm_X_RT_RA_RB(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, r%d, r%d", i.type->name, i.X.RT, i.X.RA, i.X.RB);
void Disasm_X_RT_RA_RB(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, r%d, r%d", i->type->name, i->X.RT, i->X.RA,
i->X.RB);
}
void Disasm_X_RT_RA0_RB(InstrData& i, StringBuffer* str) {
if (i.X.RA) {
str->AppendFormat("%-8s r%d, r%d, r%d", i.type->name, i.X.RT, i.X.RA,
i.X.RB);
void Disasm_X_RT_RA0_RB(InstrData* i, StringBuffer* str) {
if (i->X.RA) {
str->AppendFormat("%-8s r%d, r%d, r%d", i->type->name, i->X.RT, i->X.RA,
i->X.RB);
} else {
str->AppendFormat("%-8s r%d, 0, r%d", i.type->name, i.X.RT, i.X.RB);
str->AppendFormat("%-8s r%d, 0, r%d", i->type->name, i->X.RT, i->X.RB);
}
}
void Disasm_X_FRT_RA_RB(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s f%d, r%d, r%d", i.type->name, i.X.RT, i.X.RA, i.X.RB);
void Disasm_X_FRT_RA_RB(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s f%d, r%d, r%d", i->type->name, i->X.RT, i->X.RA,
i->X.RB);
}
void Disasm_X_FRT_RA0_RB(InstrData& i, StringBuffer* str) {
if (i.X.RA) {
str->AppendFormat("%-8s f%d, r%d, r%d", i.type->name, i.X.RT, i.X.RA,
i.X.RB);
void Disasm_X_FRT_RA0_RB(InstrData* i, StringBuffer* str) {
if (i->X.RA) {
str->AppendFormat("%-8s f%d, r%d, r%d", i->type->name, i->X.RT, i->X.RA,
i->X.RB);
} else {
str->AppendFormat("%-8s f%d, 0, r%d", i.type->name, i.X.RT, i.X.RB);
str->AppendFormat("%-8s f%d, 0, r%d", i->type->name, i->X.RT, i->X.RB);
}
}
void Disasm_D_RT_RA_I(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, r%d, %d", i.type->name, i.D.RT, i.D.RA,
(int32_t)(int16_t)XEEXTS16(i.D.DS));
void Disasm_D_RT_RA_I(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, r%d, %d", i->type->name, i->D.RT, i->D.RA,
(int32_t)(int16_t)XEEXTS16(i->D.DS));
}
void Disasm_D_RT_RA0_I(InstrData& i, StringBuffer* str) {
if (i.D.RA) {
str->AppendFormat("%-8s r%d, r%d, %d", i.type->name, i.D.RT, i.D.RA,
(int32_t)(int16_t)XEEXTS16(i.D.DS));
void Disasm_D_RT_RA0_I(InstrData* i, StringBuffer* str) {
if (i->D.RA) {
str->AppendFormat("%-8s r%d, r%d, %d", i->type->name, i->D.RT, i->D.RA,
(int32_t)(int16_t)XEEXTS16(i->D.DS));
} else {
str->AppendFormat("%-8s r%d, 0, %d", i.type->name, i.D.RT,
(int32_t)(int16_t)XEEXTS16(i.D.DS));
str->AppendFormat("%-8s r%d, 0, %d", i->type->name, i->D.RT,
(int32_t)(int16_t)XEEXTS16(i->D.DS));
}
}
void Disasm_D_FRT_RA_I(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s f%d, r%d, %d", i.type->name, i.D.RT, i.D.RA,
(int32_t)(int16_t)XEEXTS16(i.D.DS));
void Disasm_D_FRT_RA_I(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s f%d, r%d, %d", i->type->name, i->D.RT, i->D.RA,
(int32_t)(int16_t)XEEXTS16(i->D.DS));
}
void Disasm_D_FRT_RA0_I(InstrData& i, StringBuffer* str) {
if (i.D.RA) {
str->AppendFormat("%-8s f%d, r%d, %d", i.type->name, i.D.RT, i.D.RA,
(int32_t)(int16_t)XEEXTS16(i.D.DS));
void Disasm_D_FRT_RA0_I(InstrData* i, StringBuffer* str) {
if (i->D.RA) {
str->AppendFormat("%-8s f%d, r%d, %d", i->type->name, i->D.RT, i->D.RA,
(int32_t)(int16_t)XEEXTS16(i->D.DS));
} else {
str->AppendFormat("%-8s f%d, 0, %d", i.type->name, i.D.RT,
(int32_t)(int16_t)XEEXTS16(i.D.DS));
str->AppendFormat("%-8s f%d, 0, %d", i->type->name, i->D.RT,
(int32_t)(int16_t)XEEXTS16(i->D.DS));
}
}
void Disasm_DS_RT_RA_I(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, r%d, %d", i.type->name, i.DS.RT, i.DS.RA,
(int32_t)(int16_t)XEEXTS16(i.DS.DS << 2));
void Disasm_DS_RT_RA_I(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, r%d, %d", i->type->name, i->DS.RT, i->DS.RA,
(int32_t)(int16_t)XEEXTS16(i->DS.DS << 2));
}
void Disasm_DS_RT_RA0_I(InstrData& i, StringBuffer* str) {
if (i.DS.RA) {
str->AppendFormat("%-8s r%d, r%d, %d", i.type->name, i.DS.RT, i.DS.RA,
(int32_t)(int16_t)XEEXTS16(i.DS.DS << 2));
void Disasm_DS_RT_RA0_I(InstrData* i, StringBuffer* str) {
if (i->DS.RA) {
str->AppendFormat("%-8s r%d, r%d, %d", i->type->name, i->DS.RT, i->DS.RA,
(int32_t)(int16_t)XEEXTS16(i->DS.DS << 2));
} else {
str->AppendFormat("%-8s r%d, 0, %d", i.type->name, i.DS.RT,
(int32_t)(int16_t)XEEXTS16(i.DS.DS << 2));
str->AppendFormat("%-8s r%d, 0, %d", i->type->name, i->DS.RT,
(int32_t)(int16_t)XEEXTS16(i->DS.DS << 2));
}
}
void Disasm_D_RA(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s r%d", i.type->name, i.D.RA);
void Disasm_D_RA(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s r%d", i->type->name, i->D.RA);
}
void Disasm_X_RA_RB(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, r%d", i.type->name, i.X.RA, i.X.RB);
void Disasm_X_RA_RB(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, r%d", i->type->name, i->X.RA, i->X.RB);
}
void Disasm_XO_RT_RA_RB(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s%s r%d, r%d, r%d", i.XO.Rc ? -7 : -8, i.type->name,
i.XO.OE ? "o" : "", i.XO.Rc ? "." : "", i.XO.RT, i.XO.RA,
i.XO.RB);
void Disasm_XO_RT_RA_RB(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s%s r%d, r%d, r%d", i->XO.Rc ? -7 : -8, i->type->name,
i->XO.OE ? "o" : "", i->XO.Rc ? "." : "", i->XO.RT,
i->XO.RA, i->XO.RB);
}
void Disasm_XO_RT_RA(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s%s r%d, r%d", i.XO.Rc ? -7 : -8, i.type->name,
i.XO.OE ? "o" : "", i.XO.Rc ? "." : "", i.XO.RT, i.XO.RA);
void Disasm_XO_RT_RA(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s%s r%d, r%d", i->XO.Rc ? -7 : -8, i->type->name,
i->XO.OE ? "o" : "", i->XO.Rc ? "." : "", i->XO.RT,
i->XO.RA);
}
void Disasm_X_RA_RT_RB(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s r%d, r%d, r%d", i.X.Rc ? -7 : -8, i.type->name,
i.X.Rc ? "." : "", i.X.RA, i.X.RT, i.X.RB);
void Disasm_X_RA_RT_RB(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s r%d, r%d, r%d", i->X.Rc ? -7 : -8, i->type->name,
i->X.Rc ? "." : "", i->X.RA, i->X.RT, i->X.RB);
}
void Disasm_D_RA_RT_I(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-7s. r%d, r%d, %.4Xh", i.type->name, i.D.RA, i.D.RT,
i.D.DS);
void Disasm_D_RA_RT_I(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-7s. r%d, r%d, %.4Xh", i->type->name, i->D.RA, i->D.RT,
i->D.DS);
}
void Disasm_X_RA_RT(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s r%d, r%d", i.X.Rc ? -7 : -8, i.type->name,
i.X.Rc ? "." : "", i.X.RA, i.X.RT);
void Disasm_X_RA_RT(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s r%d, r%d", i->X.Rc ? -7 : -8, i->type->name,
i->X.Rc ? "." : "", i->X.RA, i->X.RT);
}
#define OP(x) ((((uint32_t)(x)) & 0x3f) << 26)
@@ -139,90 +143,90 @@ void Disasm_X_RA_RT(InstrData& i, StringBuffer* str) {
#define VX128_5(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x10))
#define VX128_P(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x630))
#define VX128_VD128 (i.VX128.VD128l | (i.VX128.VD128h << 5))
#define VX128_VD128 (i->VX128.VD128l | (i->VX128.VD128h << 5))
#define VX128_VA128 \
(i.VX128.VA128l | (i.VX128.VA128h << 5) | (i.VX128.VA128H << 6))
#define VX128_VB128 (i.VX128.VB128l | (i.VX128.VB128h << 5))
#define VX128_1_VD128 (i.VX128_1.VD128l | (i.VX128_1.VD128h << 5))
#define VX128_2_VD128 (i.VX128_2.VD128l | (i.VX128_2.VD128h << 5))
(i->VX128.VA128l | (i->VX128.VA128h << 5) | (i->VX128.VA128H << 6))
#define VX128_VB128 (i->VX128.VB128l | (i->VX128.VB128h << 5))
#define VX128_1_VD128 (i->VX128_1.VD128l | (i->VX128_1.VD128h << 5))
#define VX128_2_VD128 (i->VX128_2.VD128l | (i->VX128_2.VD128h << 5))
#define VX128_2_VA128 \
(i.VX128_2.VA128l | (i.VX128_2.VA128h << 5) | (i.VX128_2.VA128H << 6))
#define VX128_2_VB128 (i.VX128_2.VB128l | (i.VX128_2.VB128h << 5))
#define VX128_2_VC (i.VX128_2.VC)
#define VX128_3_VD128 (i.VX128_3.VD128l | (i.VX128_3.VD128h << 5))
#define VX128_3_VB128 (i.VX128_3.VB128l | (i.VX128_3.VB128h << 5))
#define VX128_3_IMM (i.VX128_3.IMM)
#define VX128_4_VD128 (i.VX128_4.VD128l | (i.VX128_4.VD128h << 5))
#define VX128_4_VB128 (i.VX128_4.VB128l | (i.VX128_4.VB128h << 5))
#define VX128_5_VD128 (i.VX128_5.VD128l | (i.VX128_5.VD128h << 5))
(i->VX128_2.VA128l | (i->VX128_2.VA128h << 5) | (i->VX128_2.VA128H << 6))
#define VX128_2_VB128 (i->VX128_2.VB128l | (i->VX128_2.VB128h << 5))
#define VX128_2_VC (i->VX128_2.VC)
#define VX128_3_VD128 (i->VX128_3.VD128l | (i->VX128_3.VD128h << 5))
#define VX128_3_VB128 (i->VX128_3.VB128l | (i->VX128_3.VB128h << 5))
#define VX128_3_IMM (i->VX128_3.IMM)
#define VX128_4_VD128 (i->VX128_4.VD128l | (i->VX128_4.VD128h << 5))
#define VX128_4_VB128 (i->VX128_4.VB128l | (i->VX128_4.VB128h << 5))
#define VX128_5_VD128 (i->VX128_5.VD128l | (i->VX128_5.VD128h << 5))
#define VX128_5_VA128 \
(i.VX128_5.VA128l | (i.VX128_5.VA128h << 5)) | (i.VX128_5.VA128H << 6)
#define VX128_5_VB128 (i.VX128_5.VB128l | (i.VX128_5.VB128h << 5))
#define VX128_5_SH (i.VX128_5.SH)
#define VX128_R_VD128 (i.VX128_R.VD128l | (i.VX128_R.VD128h << 5))
(i->VX128_5.VA128l | (i->VX128_5.VA128h << 5)) | (i->VX128_5.VA128H << 6)
#define VX128_5_VB128 (i->VX128_5.VB128l | (i->VX128_5.VB128h << 5))
#define VX128_5_SH (i->VX128_5.SH)
#define VX128_R_VD128 (i->VX128_R.VD128l | (i->VX128_R.VD128h << 5))
#define VX128_R_VA128 \
(i.VX128_R.VA128l | (i.VX128_R.VA128h << 5) | (i.VX128_R.VA128H << 6))
#define VX128_R_VB128 (i.VX128_R.VB128l | (i.VX128_R.VB128h << 5))
(i->VX128_R.VA128l | (i->VX128_R.VA128h << 5) | (i->VX128_R.VA128H << 6))
#define VX128_R_VB128 (i->VX128_R.VB128l | (i->VX128_R.VB128h << 5))
void Disasm_X_VX_RA0_RB(InstrData& i, StringBuffer* str) {
if (i.X.RA) {
str->AppendFormat("%-8s v%d, r%d, r%d", i.type->name, i.X.RT, i.X.RA,
i.X.RB);
void Disasm_X_VX_RA0_RB(InstrData* i, StringBuffer* str) {
if (i->X.RA) {
str->AppendFormat("%-8s v%d, r%d, r%d", i->type->name, i->X.RT, i->X.RA,
i->X.RB);
} else {
str->AppendFormat("%-8s v%d, 0, r%d", i.type->name, i.X.RT, i.X.RB);
str->AppendFormat("%-8s v%d, 0, r%d", i->type->name, i->X.RT, i->X.RB);
}
}
void Disasm_VX1281_VD_RA0_RB(InstrData& i, StringBuffer* str) {
void Disasm_VX1281_VD_RA0_RB(InstrData* i, StringBuffer* str) {
const uint32_t vd = VX128_1_VD128;
if (i.VX128_1.RA) {
str->AppendFormat("%-8s v%d, r%d, r%d", i.type->name, vd, i.VX128_1.RA,
i.VX128_1.RB);
if (i->VX128_1.RA) {
str->AppendFormat("%-8s v%d, r%d, r%d", i->type->name, vd, i->VX128_1.RA,
i->VX128_1.RB);
} else {
str->AppendFormat("%-8s v%d, 0, r%d", i.type->name, vd, i.VX128_1.RB);
str->AppendFormat("%-8s v%d, 0, r%d", i->type->name, vd, i->VX128_1.RB);
}
}
void Disasm_VX1283_VD_VB(InstrData& i, StringBuffer* str) {
void Disasm_VX1283_VD_VB(InstrData* i, StringBuffer* str) {
const uint32_t vd = VX128_3_VD128;
const uint32_t vb = VX128_3_VB128;
str->AppendFormat("%-8s v%d, v%d", i.type->name, vd, vb);
str->AppendFormat("%-8s v%d, v%d", i->type->name, vd, vb);
}
void Disasm_VX1283_VD_VB_I(InstrData& i, StringBuffer* str) {
void Disasm_VX1283_VD_VB_I(InstrData* i, StringBuffer* str) {
const uint32_t vd = VX128_VD128;
const uint32_t va = VX128_VA128;
const uint32_t uimm = i.VX128_3.IMM;
str->AppendFormat("%-8s v%d, v%d, %.2Xh", i.type->name, vd, va, uimm);
const uint32_t uimm = i->VX128_3.IMM;
str->AppendFormat("%-8s v%d, v%d, %.2Xh", i->type->name, vd, va, uimm);
}
void Disasm_VX_VD_VA_VB(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s v%d, v%d, v%d", i.type->name, i.VX.VD, i.VX.VA,
i.VX.VB);
void Disasm_VX_VD_VA_VB(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s v%d, v%d, v%d", i->type->name, i->VX.VD, i->VX.VA,
i->VX.VB);
}
void Disasm_VX128_VD_VA_VB(InstrData& i, StringBuffer* str) {
void Disasm_VX128_VD_VA_VB(InstrData* i, StringBuffer* str) {
const uint32_t vd = VX128_VD128;
const uint32_t va = VX128_VA128;
const uint32_t vb = VX128_VB128;
str->AppendFormat("%-8s v%d, v%d, v%d", i.type->name, vd, va, vb);
str->AppendFormat("%-8s v%d, v%d, v%d", i->type->name, vd, va, vb);
}
void Disasm_VX128_VD_VA_VD_VB(InstrData& i, StringBuffer* str) {
void Disasm_VX128_VD_VA_VD_VB(InstrData* i, StringBuffer* str) {
const uint32_t vd = VX128_VD128;
const uint32_t va = VX128_VA128;
const uint32_t vb = VX128_VB128;
str->AppendFormat("%-8s v%d, v%d, v%d, v%d", i.type->name, vd, va, vd, vb);
str->AppendFormat("%-8s v%d, v%d, v%d, v%d", i->type->name, vd, va, vd, vb);
}
void Disasm_VX1282_VD_VA_VB_VC(InstrData& i, StringBuffer* str) {
void Disasm_VX1282_VD_VA_VB_VC(InstrData* i, StringBuffer* str) {
const uint32_t vd = VX128_2_VD128;
const uint32_t va = VX128_2_VA128;
const uint32_t vb = VX128_2_VB128;
const uint32_t vc = i.VX128_2.VC;
str->AppendFormat("%-8s v%d, v%d, v%d, v%d", i.type->name, vd, va, vb, vc);
const uint32_t vc = i->VX128_2.VC;
str->AppendFormat("%-8s v%d, v%d, v%d, v%d", i->type->name, vd, va, vb, vc);
}
void Disasm_VXA_VD_VA_VB_VC(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s v%d, v%d, v%d, v%d", i.type->name, i.VXA.VD, i.VXA.VA,
i.VXA.VB, i.VXA.VC);
void Disasm_VXA_VD_VA_VB_VC(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s v%d, v%d, v%d, v%d", i->type->name, i->VXA.VD,
i->VXA.VA, i->VXA.VB, i->VXA.VC);
}
void Disasm_sync(InstrData& i, StringBuffer* str) {
void Disasm_sync(InstrData* i, StringBuffer* str) {
const char* name;
int L = i.X.RT & 3;
int L = i->X.RT & 3;
switch (L) {
case 0:
name = "hwsync";
@@ -239,9 +243,9 @@ void Disasm_sync(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s %.2X", name, L);
}
void Disasm_dcbf(InstrData& i, StringBuffer* str) {
void Disasm_dcbf(InstrData* i, StringBuffer* str) {
const char* name;
switch (i.X.RT & 3) {
switch (i->X.RT & 3) {
case 0:
name = "dcbf";
break;
@@ -258,90 +262,90 @@ void Disasm_dcbf(InstrData& i, StringBuffer* str) {
name = "dcbf.??";
break;
}
str->AppendFormat("%-8s r%d, r%d", name, i.X.RA, i.X.RB);
str->AppendFormat("%-8s r%d, r%d", name, i->X.RA, i->X.RB);
}
void Disasm_dcbz(InstrData& i, StringBuffer* str) {
void Disasm_dcbz(InstrData* i, StringBuffer* str) {
// or dcbz128 0x7C2007EC
if (i.X.RA) {
str->AppendFormat("%-8s r%d, r%d", i.type->name, i.X.RA, i.X.RB);
if (i->X.RA) {
str->AppendFormat("%-8s r%d, r%d", i->type->name, i->X.RA, i->X.RB);
} else {
str->AppendFormat("%-8s 0, r%d", i.type->name, i.X.RB);
str->AppendFormat("%-8s 0, r%d", i->type->name, i->X.RB);
}
}
void Disasm_fcmp(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s cr%d, f%d, f%d", i.type->name, i.X.RT >> 2, i.X.RA,
i.X.RB);
void Disasm_fcmp(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s cr%d, f%d, f%d", i->type->name, i->X.RT >> 2, i->X.RA,
i->X.RB);
}
void Disasm_mffsx(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s f%d, FPSCR", i.X.Rc ? -7 : -8, i.type->name,
i.X.Rc ? "." : "", i.X.RT);
void Disasm_mffsx(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s f%d, FPSCR", i->X.Rc ? -7 : -8, i->type->name,
i->X.Rc ? "." : "", i->X.RT);
}
void Disasm_bx(InstrData& i, StringBuffer* str) {
const char* name = i.I.LK ? "bl" : "b";
void Disasm_bx(InstrData* i, StringBuffer* str) {
const char* name = i->I.LK ? "bl" : "b";
uint32_t nia;
if (i.I.AA) {
nia = (uint32_t)XEEXTS26(i.I.LI << 2);
if (i->I.AA) {
nia = (uint32_t)XEEXTS26(i->I.LI << 2);
} else {
nia = (uint32_t)(i.address + XEEXTS26(i.I.LI << 2));
nia = (uint32_t)(i->address + XEEXTS26(i->I.LI << 2));
}
str->AppendFormat("%-8s %.8X", name, nia);
// TODO(benvanik): resolve target name?
}
void Disasm_bcx(InstrData& i, StringBuffer* str) {
const char* s0 = i.B.LK ? "lr, " : "";
void Disasm_bcx(InstrData* i, StringBuffer* str) {
const char* s0 = i->B.LK ? "lr, " : "";
const char* s1;
if (!select_bits(i.B.BO, 2, 2)) {
if (!select_bits(i->B.BO, 2, 2)) {
s1 = "ctr, ";
} else {
s1 = "";
}
char s2[8] = {0};
if (!select_bits(i.B.BO, 4, 4)) {
snprintf(s2, xe::countof(s2), "cr%d, ", i.B.BI >> 2);
if (!select_bits(i->B.BO, 4, 4)) {
snprintf(s2, xe::countof(s2), "cr%d, ", i->B.BI >> 2);
}
uint32_t nia;
if (i.B.AA) {
nia = (uint32_t)XEEXTS16(i.B.BD << 2);
if (i->B.AA) {
nia = (uint32_t)XEEXTS16(i->B.BD << 2);
} else {
nia = (uint32_t)(i.address + XEEXTS16(i.B.BD << 2));
nia = (uint32_t)(i->address + XEEXTS16(i->B.BD << 2));
}
str->AppendFormat("%-8s %s%s%s%.8X", i.type->name, s0, s1, s2, nia);
str->AppendFormat("%-8s %s%s%s%.8X", i->type->name, s0, s1, s2, nia);
// TODO(benvanik): resolve target name?
}
void Disasm_bcctrx(InstrData& i, StringBuffer* str) {
void Disasm_bcctrx(InstrData* i, StringBuffer* str) {
// TODO(benvanik): mnemonics
const char* s0 = i.XL.LK ? "lr, " : "";
const char* s0 = i->XL.LK ? "lr, " : "";
char s2[8] = {0};
if (!select_bits(i.XL.BO, 4, 4)) {
snprintf(s2, xe::countof(s2), "cr%d, ", i.XL.BI >> 2);
if (!select_bits(i->XL.BO, 4, 4)) {
snprintf(s2, xe::countof(s2), "cr%d, ", i->XL.BI >> 2);
}
str->AppendFormat("%-8s %s%sctr", i.type->name, s0, s2);
str->AppendFormat("%-8s %s%sctr", i->type->name, s0, s2);
// TODO(benvanik): resolve target name?
}
void Disasm_bclrx(InstrData& i, StringBuffer* str) {
void Disasm_bclrx(InstrData* i, StringBuffer* str) {
const char* name = "bclr";
if (i.code == 0x4E800020) {
if (i->code == 0x4E800020) {
name = "blr";
}
const char* s1;
if (!select_bits(i.XL.BO, 2, 2)) {
if (!select_bits(i->XL.BO, 2, 2)) {
s1 = "ctr, ";
} else {
s1 = "";
}
char s2[8] = {0};
if (!select_bits(i.XL.BO, 4, 4)) {
snprintf(s2, xe::countof(s2), "cr%d, ", i.XL.BI >> 2);
if (!select_bits(i->XL.BO, 4, 4)) {
snprintf(s2, xe::countof(s2), "cr%d, ", i->XL.BI >> 2);
}
str->AppendFormat("%-8s %s%s", name, s1, s2);
}
void Disasm_mfcr(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, cr", i.type->name, i.X.RT);
void Disasm_mfcr(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, cr", i->type->name, i->X.RT);
}
const char* Disasm_spr_name(uint32_t n) {
const char* reg = "???";
@@ -358,154 +362,154 @@ const char* Disasm_spr_name(uint32_t n) {
}
return reg;
}
void Disasm_mfspr(InstrData& i, StringBuffer* str) {
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
void Disasm_mfspr(InstrData* i, StringBuffer* str) {
const uint32_t n = ((i->XFX.spr & 0x1F) << 5) | ((i->XFX.spr >> 5) & 0x1F);
const char* reg = Disasm_spr_name(n);
str->AppendFormat("%-8s r%d, %s", i.type->name, i.XFX.RT, reg);
str->AppendFormat("%-8s r%d, %s", i->type->name, i->XFX.RT, reg);
}
void Disasm_mtspr(InstrData& i, StringBuffer* str) {
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
void Disasm_mtspr(InstrData* i, StringBuffer* str) {
const uint32_t n = ((i->XFX.spr & 0x1F) << 5) | ((i->XFX.spr >> 5) & 0x1F);
const char* reg = Disasm_spr_name(n);
str->AppendFormat("%-8s %s, r%d", i.type->name, reg, i.XFX.RT);
str->AppendFormat("%-8s %s, r%d", i->type->name, reg, i->XFX.RT);
}
void Disasm_mftb(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, tb", i.type->name, i.XFX.RT);
void Disasm_mftb(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, tb", i->type->name, i->XFX.RT);
}
void Disasm_mfmsr(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s r%d", i.type->name, i.X.RT);
void Disasm_mfmsr(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s r%d", i->type->name, i->X.RT);
}
void Disasm_mtmsr(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, %d", i.type->name, i.X.RT,
(i.X.RA & 16) ? 1 : 0);
void Disasm_mtmsr(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s r%d, %d", i->type->name, i->X.RT,
(i->X.RA & 16) ? 1 : 0);
}
void Disasm_cmp(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s cr%d, %.2X, r%d, r%d", i.type->name, i.X.RT >> 2,
i.X.RT & 1, i.X.RA, i.X.RB);
void Disasm_cmp(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s cr%d, %.2X, r%d, r%d", i->type->name, i->X.RT >> 2,
i->X.RT & 1, i->X.RA, i->X.RB);
}
void Disasm_cmpi(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s cr%d, %.2X, r%d, %d", i.type->name, i.D.RT >> 2,
i.D.RT & 1, i.D.RA, XEEXTS16(i.D.DS));
void Disasm_cmpi(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s cr%d, %.2X, r%d, %d", i->type->name, i->D.RT >> 2,
i->D.RT & 1, i->D.RA, XEEXTS16(i->D.DS));
}
void Disasm_cmpli(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s cr%d, %.2X, r%d, %.2X", i.type->name, i.D.RT >> 2,
i.D.RT & 1, i.D.RA, XEEXTS16(i.D.DS));
void Disasm_cmpli(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s cr%d, %.2X, r%d, %.2X", i->type->name, i->D.RT >> 2,
i->D.RT & 1, i->D.RA, XEEXTS16(i->D.DS));
}
void Disasm_rld(InstrData& i, StringBuffer* str) {
if (i.MD.idx == 0) {
void Disasm_rld(InstrData* i, StringBuffer* str) {
if (i->MD.idx == 0) {
// XEDISASMR(rldiclx, 0x78000000, MD )
str->AppendFormat("%*s%s r%d, r%d, %d, %d", i.MD.Rc ? -7 : -8, "rldicl",
i.MD.Rc ? "." : "", i.MD.RA, i.MD.RT,
(i.MD.SH5 << 5) | i.MD.SH, (i.MD.MB5 << 5) | i.MD.MB);
} else if (i.MD.idx == 1) {
str->AppendFormat("%*s%s r%d, r%d, %d, %d", i->MD.Rc ? -7 : -8, "rldicl",
i->MD.Rc ? "." : "", i->MD.RA, i->MD.RT,
(i->MD.SH5 << 5) | i->MD.SH, (i->MD.MB5 << 5) | i->MD.MB);
} else if (i->MD.idx == 1) {
// XEDISASMR(rldicrx, 0x78000004, MD )
str->AppendFormat("%*s%s r%d, r%d, %d, %d", i.MD.Rc ? -7 : -8, "rldicr",
i.MD.Rc ? "." : "", i.MD.RA, i.MD.RT,
(i.MD.SH5 << 5) | i.MD.SH, (i.MD.MB5 << 5) | i.MD.MB);
} else if (i.MD.idx == 2) {
str->AppendFormat("%*s%s r%d, r%d, %d, %d", i->MD.Rc ? -7 : -8, "rldicr",
i->MD.Rc ? "." : "", i->MD.RA, i->MD.RT,
(i->MD.SH5 << 5) | i->MD.SH, (i->MD.MB5 << 5) | i->MD.MB);
} else if (i->MD.idx == 2) {
// XEDISASMR(rldicx, 0x78000008, MD )
uint32_t sh = (i.MD.SH5 << 5) | i.MD.SH;
uint32_t mb = (i.MD.MB5 << 5) | i.MD.MB;
uint32_t sh = (i->MD.SH5 << 5) | i->MD.SH;
uint32_t mb = (i->MD.MB5 << 5) | i->MD.MB;
const char* name = (mb == 0x3E) ? "sldi" : "rldic";
str->AppendFormat("%*s%s r%d, r%d, %d, %d", i.MD.Rc ? -7 : -8, name,
i.MD.Rc ? "." : "", i.MD.RA, i.MD.RT, sh, mb);
} else if (i.MDS.idx == 8) {
str->AppendFormat("%*s%s r%d, r%d, %d, %d", i->MD.Rc ? -7 : -8, name,
i->MD.Rc ? "." : "", i->MD.RA, i->MD.RT, sh, mb);
} else if (i->MDS.idx == 8) {
// XEDISASMR(rldclx, 0x78000010, MDS)
str->AppendFormat("%*s%s r%d, r%d, %d, %d", i.MDS.Rc ? -7 : -8, "rldcl",
i.MDS.Rc ? "." : "", i.MDS.RA, i.MDS.RT, i.MDS.RB,
(i.MDS.MB5 << 5) | i.MDS.MB);
} else if (i.MDS.idx == 9) {
str->AppendFormat("%*s%s r%d, r%d, %d, %d", i->MDS.Rc ? -7 : -8, "rldcl",
i->MDS.Rc ? "." : "", i->MDS.RA, i->MDS.RT, i->MDS.RB,
(i->MDS.MB5 << 5) | i->MDS.MB);
} else if (i->MDS.idx == 9) {
// XEDISASMR(rldcrx, 0x78000012, MDS)
str->AppendFormat("%*s%s r%d, r%d, %d, %d", i.MDS.Rc ? -7 : -8, "rldcr",
i.MDS.Rc ? "." : "", i.MDS.RA, i.MDS.RT, i.MDS.RB,
(i.MDS.MB5 << 5) | i.MDS.MB);
} else if (i.MD.idx == 3) {
str->AppendFormat("%*s%s r%d, r%d, %d, %d", i->MDS.Rc ? -7 : -8, "rldcr",
i->MDS.Rc ? "." : "", i->MDS.RA, i->MDS.RT, i->MDS.RB,
(i->MDS.MB5 << 5) | i->MDS.MB);
} else if (i->MD.idx == 3) {
// XEDISASMR(rldimix, 0x7800000C, MD )
str->AppendFormat("%*s%s r%d, r%d, %d, %d", i.MD.Rc ? -7 : -8, "rldimi",
i.MD.Rc ? "." : "", i.MD.RA, i.MD.RT,
(i.MD.SH5 << 5) | i.MD.SH, (i.MD.MB5 << 5) | i.MD.MB);
str->AppendFormat("%*s%s r%d, r%d, %d, %d", i->MD.Rc ? -7 : -8, "rldimi",
i->MD.Rc ? "." : "", i->MD.RA, i->MD.RT,
(i->MD.SH5 << 5) | i->MD.SH, (i->MD.MB5 << 5) | i->MD.MB);
} else {
assert_always();
}
}
void Disasm_rlwim(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s r%d, r%d, %d, %d, %d", i.M.Rc ? -7 : -8,
i.type->name, i.M.Rc ? "." : "", i.M.RA, i.M.RT, i.M.SH,
i.M.MB, i.M.ME);
void Disasm_rlwim(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s r%d, r%d, %d, %d, %d", i->M.Rc ? -7 : -8,
i->type->name, i->M.Rc ? "." : "", i->M.RA, i->M.RT,
i->M.SH, i->M.MB, i->M.ME);
}
void Disasm_rlwnmx(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s r%d, r%d, r%d, %d, %d", i.M.Rc ? -7 : -8,
i.type->name, i.M.Rc ? "." : "", i.M.RA, i.M.RT, i.M.SH,
i.M.MB, i.M.ME);
void Disasm_rlwnmx(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s r%d, r%d, r%d, %d, %d", i->M.Rc ? -7 : -8,
i->type->name, i->M.Rc ? "." : "", i->M.RA, i->M.RT,
i->M.SH, i->M.MB, i->M.ME);
}
void Disasm_srawix(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s r%d, r%d, %d", i.X.Rc ? -7 : -8, i.type->name,
i.X.Rc ? "." : "", i.X.RA, i.X.RT, i.X.RB);
void Disasm_srawix(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s r%d, r%d, %d", i->X.Rc ? -7 : -8, i->type->name,
i->X.Rc ? "." : "", i->X.RA, i->X.RT, i->X.RB);
}
void Disasm_sradix(InstrData& i, StringBuffer* str) {
str->AppendFormat("%*s%s r%d, r%d, %d", i.XS.Rc ? -7 : -8, i.type->name,
i.XS.Rc ? "." : "", i.XS.RA, i.XS.RT,
(i.XS.SH5 << 5) | i.XS.SH);
void Disasm_sradix(InstrData* i, StringBuffer* str) {
str->AppendFormat("%*s%s r%d, r%d, %d", i->XS.Rc ? -7 : -8, i->type->name,
i->XS.Rc ? "." : "", i->XS.RA, i->XS.RT,
(i->XS.SH5 << 5) | i->XS.SH);
}
void Disasm_vpermwi128(InstrData& i, StringBuffer* str) {
const uint32_t vd = i.VX128_P.VD128l | (i.VX128_P.VD128h << 5);
const uint32_t vb = i.VX128_P.VB128l | (i.VX128_P.VB128h << 5);
str->AppendFormat("%-8s v%d, v%d, %.2X", i.type->name, vd, vb,
i.VX128_P.PERMl | (i.VX128_P.PERMh << 5));
void Disasm_vpermwi128(InstrData* i, StringBuffer* str) {
const uint32_t vd = i->VX128_P.VD128l | (i->VX128_P.VD128h << 5);
const uint32_t vb = i->VX128_P.VB128l | (i->VX128_P.VB128h << 5);
str->AppendFormat("%-8s v%d, v%d, %.2X", i->type->name, vd, vb,
i->VX128_P.PERMl | (i->VX128_P.PERMh << 5));
}
void Disasm_vrfin128(InstrData& i, StringBuffer* str) {
void Disasm_vrfin128(InstrData* i, StringBuffer* str) {
const uint32_t vd = VX128_3_VD128;
const uint32_t vb = VX128_3_VB128;
str->AppendFormat("%-8s v%d, v%d", i.type->name, vd, vb);
str->AppendFormat("%-8s v%d, v%d", i->type->name, vd, vb);
}
void Disasm_vrlimi128(InstrData& i, StringBuffer* str) {
void Disasm_vrlimi128(InstrData* i, StringBuffer* str) {
const uint32_t vd = VX128_4_VD128;
const uint32_t vb = VX128_4_VB128;
str->AppendFormat("%-8s v%d, v%d, %.2X, %.2X", i.type->name, vd, vb,
i.VX128_4.IMM, i.VX128_4.z);
str->AppendFormat("%-8s v%d, v%d, %.2X, %.2X", i->type->name, vd, vb,
i->VX128_4.IMM, i->VX128_4.z);
}
void Disasm_vsldoi128(InstrData& i, StringBuffer* str) {
void Disasm_vsldoi128(InstrData* i, StringBuffer* str) {
const uint32_t vd = VX128_5_VD128;
const uint32_t va = VX128_5_VA128;
const uint32_t vb = VX128_5_VB128;
const uint32_t sh = i.VX128_5.SH;
str->AppendFormat("%-8s v%d, v%d, v%d, %.2X", i.type->name, vd, va, vb, sh);
const uint32_t sh = i->VX128_5.SH;
str->AppendFormat("%-8s v%d, v%d, v%d, %.2X", i->type->name, vd, va, vb, sh);
}
void Disasm_vspltb(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s v%d, v%d, %.2X", i.type->name, i.VX.VD, i.VX.VB,
i.VX.VA & 0xF);
void Disasm_vspltb(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s v%d, v%d, %.2X", i->type->name, i->VX.VD, i->VX.VB,
i->VX.VA & 0xF);
}
void Disasm_vsplth(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s v%d, v%d, %.2X", i.type->name, i.VX.VD, i.VX.VB,
i.VX.VA & 0x7);
void Disasm_vsplth(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s v%d, v%d, %.2X", i->type->name, i->VX.VD, i->VX.VB,
i->VX.VA & 0x7);
}
void Disasm_vspltw(InstrData& i, StringBuffer* str) {
str->AppendFormat("%-8s v%d, v%d, %.2X", i.type->name, i.VX.VD, i.VX.VB,
i.VX.VA);
void Disasm_vspltw(InstrData* i, StringBuffer* str) {
str->AppendFormat("%-8s v%d, v%d, %.2X", i->type->name, i->VX.VD, i->VX.VB,
i->VX.VA);
}
void Disasm_vspltisb(InstrData& i, StringBuffer* str) {
void Disasm_vspltisb(InstrData* i, StringBuffer* str) {
// 5bit -> 8bit sign extend
int8_t simm = (i.VX.VA & 0x10) ? (i.VX.VA | 0xF0) : i.VX.VA;
str->AppendFormat("%-8s v%d, %.2X", i.type->name, i.VX.VD, simm);
int8_t simm = (i->VX.VA & 0x10) ? (i->VX.VA | 0xF0) : i->VX.VA;
str->AppendFormat("%-8s v%d, %.2X", i->type->name, i->VX.VD, simm);
}
void Disasm_vspltish(InstrData& i, StringBuffer* str) {
void Disasm_vspltish(InstrData* i, StringBuffer* str) {
// 5bit -> 16bit sign extend
int16_t simm = (i.VX.VA & 0x10) ? (i.VX.VA | 0xFFF0) : i.VX.VA;
str->AppendFormat("%-8s v%d, %.4X", i.type->name, i.VX.VD, simm);
int16_t simm = (i->VX.VA & 0x10) ? (i->VX.VA | 0xFFF0) : i->VX.VA;
str->AppendFormat("%-8s v%d, %.4X", i->type->name, i->VX.VD, simm);
}
void Disasm_vspltisw(InstrData& i, StringBuffer* str) {
void Disasm_vspltisw(InstrData* i, StringBuffer* str) {
// 5bit -> 32bit sign extend
int32_t simm = (i.VX.VA & 0x10) ? (i.VX.VA | 0xFFFFFFF0) : i.VX.VA;
str->AppendFormat("%-8s v%d, %.8X", i.type->name, i.VX.VD, simm);
int32_t simm = (i->VX.VA & 0x10) ? (i->VX.VA | 0xFFFFFFF0) : i->VX.VA;
str->AppendFormat("%-8s v%d, %.8X", i->type->name, i->VX.VD, simm);
}
int DisasmPPC(InstrData& i, StringBuffer* str) {
if (!i.type) {
int DisasmPPC(InstrData* i, StringBuffer* str) {
if (!i->type) {
str->Append("???");
} else {
i.type->disasm(i, str);
i->type->disasm(i, str);
}
return 0;
}

8
src/xenia/cpu/frontend/ppc_disasm.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_FRONTEND_PPC_DISASM_H_
#define XENIA_FRONTEND_PPC_DISASM_H_
#ifndef XENIA_CPU_FRONTEND_PPC_DISASM_H_
#define XENIA_CPU_FRONTEND_PPC_DISASM_H_
#include "xenia/base/string_buffer.h"
#include "xenia/cpu/frontend/ppc_instr.h"
@@ -17,10 +17,10 @@ namespace xe {
namespace cpu {
namespace frontend {
int DisasmPPC(InstrData& i, StringBuffer* str);
int DisasmPPC(InstrData* i, StringBuffer* str);
} // namespace frontend
} // namespace cpu
} // namespace xe
#endif // XENIA_FRONTEND_PPC_DISASM_H_
#endif // XENIA_CPU_FRONTEND_PPC_DISASM_H_

8
src/xenia/cpu/frontend/ppc_emit-private.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_FRONTEND_PPC_EMIT_PRIVATE_H_
#define XENIA_FRONTEND_PPC_EMIT_PRIVATE_H_
#ifndef XENIA_CPU_FRONTEND_PPC_EMIT_PRIVATE_H_
#define XENIA_CPU_FRONTEND_PPC_EMIT_PRIVATE_H_
#include "xenia/cpu/frontend/ppc_emit.h"
#include "xenia/cpu/frontend/ppc_instr.h"
@@ -22,12 +22,10 @@ namespace frontend {
#define XEREGISTERINSTR(name, opcode) \
RegisterInstrEmit(opcode, (InstrEmitFn)InstrEmit_##name);
//#define XEINSTRNOTIMPLEMENTED()
#define XEINSTRNOTIMPLEMENTED() assert_always("Instruction not implemented");
//#define XEINSTRNOTIMPLEMENTED() __debugbreak()
} // namespace frontend
} // namespace cpu
} // namespace xe
#endif // XENIA_FRONTEND_PPC_EMIT_PRIVATE_H_
#endif // XENIA_CPU_FRONTEND_PPC_EMIT_PRIVATE_H_

6
src/xenia/cpu/frontend/ppc_emit.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_FRONTEND_PPC_EMIT_H_
#define XENIA_FRONTEND_PPC_EMIT_H_
#ifndef XENIA_CPU_FRONTEND_PPC_EMIT_H_
#define XENIA_CPU_FRONTEND_PPC_EMIT_H_
#include "xenia/cpu/frontend/ppc_instr.h"
@@ -26,4 +26,4 @@ void RegisterEmitCategoryMemory();
} // namespace cpu
} // namespace xe
#endif // XENIA_FRONTEND_PPC_EMIT_H_
#endif // XENIA_CPU_FRONTEND_PPC_EMIT_H_

34
src/xenia/cpu/frontend/ppc_emit_altivec.cc
View File

@@ -987,7 +987,7 @@ int InstrEmit_vmrghw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
// (VD.z) = (VA.y)
// (VD.w) = (VB.y)
Value* v =
f.Permute(f.LoadConstantUint32(PERMUTE_MASK(0, 0, 1, 0, 0, 1, 1, 1)),
f.Permute(f.LoadConstantUint32(MakePermuteMask(0, 0, 1, 0, 0, 1, 1, 1)),
f.LoadVR(va), f.LoadVR(vb), INT32_TYPE);
f.StoreVR(vd, v);
return 0;
@@ -1028,7 +1028,7 @@ int InstrEmit_vmrglw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
// (VD.z) = (VA.w)
// (VD.w) = (VB.w)
Value* v =
f.Permute(f.LoadConstantUint32(PERMUTE_MASK(0, 2, 1, 2, 0, 3, 1, 3)),
f.Permute(f.LoadConstantUint32(MakePermuteMask(0, 2, 1, 2, 0, 3, 1, 3)),
f.LoadVR(va), f.LoadVR(vb), INT32_TYPE);
f.StoreVR(vd, v);
return 0;
@@ -1206,7 +1206,7 @@ XEEMITTER(vpermwi128, VX128_P(6, 528), VX128_P)(PPCHIRBuilder& f,
const uint32_t vd = i.VX128_P.VD128l | (i.VX128_P.VD128h << 5);
const uint32_t vb = i.VX128_P.VB128l | (i.VX128_P.VB128h << 5);
uint32_t uimm = i.VX128_P.PERMl | (i.VX128_P.PERMh << 5);
uint32_t mask = SWIZZLE_MASK(uimm >> 6, uimm >> 4, uimm >> 2, uimm >> 0);
uint32_t mask = MakeSwizzleMask(uimm >> 6, uimm >> 4, uimm >> 2, uimm >> 0);
Value* v = f.Swizzle(f.LoadVR(vb), INT32_TYPE, mask);
f.StoreVR(vd, v);
return 0;
@@ -1347,7 +1347,7 @@ XEEMITTER(vrlimi128, VX128_4(6, 1808), VX128_4)(PPCHIRBuilder& f,
} else {
v = f.LoadVR(vb);
}
if (blend_mask != PERMUTE_IDENTITY) {
if (blend_mask != kIdentityPermuteMask) {
v = f.Permute(f.LoadConstantUint32(blend_mask), v, f.LoadVR(vd),
INT32_TYPE);
}
@@ -2053,22 +2053,22 @@ XEEMITTER(vpkd3d128, VX128_4(6, 1552), VX128_4)(PPCHIRBuilder& f,
}
// http://hlssmod.net/he_code/public/pixelwriter.h
// control = prev:0123 | new:4567
uint32_t control = PERMUTE_IDENTITY; // original
uint32_t control = kIdentityPermuteMask; // original
switch (pack) {
case 1: // VPACK_32
// VPACK_32 & shift = 3 puts lower 32 bits in x (leftmost slot).
switch (shift) {
case 0:
control = PERMUTE_MASK(0, 0, 0, 1, 0, 2, 1, 3);
control = MakePermuteMask(0, 0, 0, 1, 0, 2, 1, 3);
break;
case 1:
control = PERMUTE_MASK(0, 0, 0, 1, 1, 3, 0, 3);
control = MakePermuteMask(0, 0, 0, 1, 1, 3, 0, 3);
break;
case 2:
control = PERMUTE_MASK(0, 0, 1, 3, 0, 2, 0, 3);
control = MakePermuteMask(0, 0, 1, 3, 0, 2, 0, 3);
break;
case 3:
control = PERMUTE_MASK(1, 3, 0, 1, 0, 2, 0, 3);
control = MakePermuteMask(1, 3, 0, 1, 0, 2, 0, 3);
break;
default:
assert_unhandled_case(shift);
@@ -2078,16 +2078,16 @@ XEEMITTER(vpkd3d128, VX128_4(6, 1552), VX128_4)(PPCHIRBuilder& f,
case 2: // 64bit
switch (shift) {
case 0:
control = PERMUTE_MASK(0, 0, 0, 1, 1, 2, 1, 3);
control = MakePermuteMask(0, 0, 0, 1, 1, 2, 1, 3);
break;
case 1:
control = PERMUTE_MASK(0, 0, 1, 2, 1, 3, 0, 3);
control = MakePermuteMask(0, 0, 1, 2, 1, 3, 0, 3);
break;
case 2:
control = PERMUTE_MASK(1, 2, 1, 3, 0, 2, 0, 3);
control = MakePermuteMask(1, 2, 1, 3, 0, 2, 0, 3);
break;
case 3:
control = PERMUTE_MASK(1, 3, 0, 1, 0, 2, 0, 3);
control = MakePermuteMask(1, 3, 0, 1, 0, 2, 0, 3);
break;
default:
assert_unhandled_case(shift);
@@ -2097,16 +2097,16 @@ XEEMITTER(vpkd3d128, VX128_4(6, 1552), VX128_4)(PPCHIRBuilder& f,
case 3: // 64bit
switch (shift) {
case 0:
control = PERMUTE_MASK(0, 0, 0, 1, 1, 2, 1, 3);
control = MakePermuteMask(0, 0, 0, 1, 1, 2, 1, 3);
break;
case 1:
control = PERMUTE_MASK(0, 0, 1, 2, 1, 3, 0, 3);
control = MakePermuteMask(0, 0, 1, 2, 1, 3, 0, 3);
break;
case 2:
control = PERMUTE_MASK(1, 2, 1, 3, 0, 2, 0, 3);
control = MakePermuteMask(1, 2, 1, 3, 0, 2, 0, 3);
break;
case 3:
control = PERMUTE_MASK(0, 0, 0, 1, 0, 2, 1, 2);
control = MakePermuteMask(0, 0, 0, 1, 0, 2, 1, 2);
break;
default:
assert_unhandled_case(shift);

6
src/xenia/cpu/frontend/ppc_frontend.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_FRONTEND_PPC_FRONTEND_H_
#define XENIA_FRONTEND_PPC_FRONTEND_H_
#ifndef XENIA_CPU_FRONTEND_PPC_FRONTEND_H_
#define XENIA_CPU_FRONTEND_PPC_FRONTEND_H_
#include <memory>
#include <mutex>
@@ -64,4 +64,4 @@ class PPCFrontend {
} // namespace cpu
} // namespace xe
#endif // XENIA_FRONTEND_PPC_FRONTEND_H_
#endif // XENIA_CPU_FRONTEND_PPC_FRONTEND_H_

2
src/xenia/cpu/frontend/ppc_hir_builder.cc
View File

@@ -106,7 +106,7 @@ bool PPCHIRBuilder::Emit(GuestFunction* function, uint32_t flags) {
}
comment_buffer_.Reset();
comment_buffer_.AppendFormat("%.8X %.8X ", address, i.code);
DisasmPPC(i, &comment_buffer_);
DisasmPPC(&i, &comment_buffer_);
Comment(comment_buffer_);
first_instr = last_instr();
}

8
src/xenia/cpu/frontend/ppc_hir_builder.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_FRONTEND_PPC_HIR_BUILDER_H_
#define XENIA_FRONTEND_PPC_HIR_BUILDER_H_
#ifndef XENIA_CPU_FRONTEND_PPC_HIR_BUILDER_H_
#define XENIA_CPU_FRONTEND_PPC_HIR_BUILDER_H_
#include "xenia/base/string_buffer.h"
#include "xenia/cpu/hir/hir_builder.h"
@@ -26,7 +26,7 @@ class PPCHIRBuilder : public hir::HIRBuilder {
using Value = xe::cpu::hir::Value;
public:
PPCHIRBuilder(PPCFrontend* frontend);
explicit PPCHIRBuilder(PPCFrontend* frontend);
~PPCHIRBuilder() override;
void Reset() override;
@@ -109,4 +109,4 @@ class PPCHIRBuilder : public hir::HIRBuilder {
} // namespace cpu
} // namespace xe
#endif // XENIA_FRONTEND_PPC_HIR_BUILDER_H_
#endif // XENIA_CPU_FRONTEND_PPC_HIR_BUILDER_H_

8
src/xenia/cpu/frontend/ppc_instr.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_FRONTEND_PPC_INSTR_H_
#define XENIA_FRONTEND_PPC_INSTR_H_
#ifndef XENIA_CPU_FRONTEND_PPC_INSTR_H_
#define XENIA_CPU_FRONTEND_PPC_INSTR_H_
#include <cstdint>
#include <string>
@@ -497,7 +497,7 @@ class InstrDisasm {
void Dump(std::string& out_str, size_t pad = 13);
};
typedef void (*InstrDisasmFn)(InstrData& i, StringBuffer* str);
typedef void (*InstrDisasmFn)(InstrData* i, StringBuffer* str);
typedef void* InstrEmitFn;
class InstrType {
@@ -522,4 +522,4 @@ int RegisterInstrEmit(uint32_t code, InstrEmitFn emit);
} // namespace cpu
} // namespace xe
#endif // XENIA_FRONTEND_PPC_INSTR_H_
#endif // XENIA_CPU_FRONTEND_PPC_INSTR_H_

134
src/xenia/cpu/frontend/ppc_instr_tables.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_FRONTEND_PPC_INSTR_TABLES_H_
#define XENIA_FRONTEND_PPC_INSTR_TABLES_H_
#ifndef XENIA_CPU_FRONTEND_PPC_INSTR_TABLES_H_
#define XENIA_CPU_FRONTEND_PPC_INSTR_TABLES_H_
#include <cmath>
@@ -20,76 +20,76 @@ namespace xe {
namespace cpu {
namespace frontend {
void Disasm_0(InstrData& i, StringBuffer* str);
void Disasm__(InstrData& i, StringBuffer* str);
void Disasm_X_FRT_FRB(InstrData& i, StringBuffer* str);
void Disasm_A_FRT_FRB(InstrData& i, StringBuffer* str);
void Disasm_A_FRT_FRA_FRB(InstrData& i, StringBuffer* str);
void Disasm_A_FRT_FRA_FRB_FRC(InstrData& i, StringBuffer* str);
void Disasm_X_RT_RA_RB(InstrData& i, StringBuffer* str);
void Disasm_X_RT_RA0_RB(InstrData& i, StringBuffer* str);
void Disasm_X_FRT_RA_RB(InstrData& i, StringBuffer* str);
void Disasm_X_FRT_RA0_RB(InstrData& i, StringBuffer* str);
void Disasm_D_RT_RA_I(InstrData& i, StringBuffer* str);
void Disasm_D_RT_RA0_I(InstrData& i, StringBuffer* str);
void Disasm_D_FRT_RA_I(InstrData& i, StringBuffer* str);
void Disasm_D_FRT_RA0_I(InstrData& i, StringBuffer* str);
void Disasm_DS_RT_RA_I(InstrData& i, StringBuffer* str);
void Disasm_DS_RT_RA0_I(InstrData& i, StringBuffer* str);
void Disasm_D_RA(InstrData& i, StringBuffer* str);
void Disasm_X_RA_RB(InstrData& i, StringBuffer* str);
void Disasm_XO_RT_RA_RB(InstrData& i, StringBuffer* str);
void Disasm_XO_RT_RA(InstrData& i, StringBuffer* str);
void Disasm_X_RA_RT_RB(InstrData& i, StringBuffer* str);
void Disasm_D_RA_RT_I(InstrData& i, StringBuffer* str);
void Disasm_X_RA_RT(InstrData& i, StringBuffer* str);
void Disasm_X_VX_RA0_RB(InstrData& i, StringBuffer* str);
void Disasm_VX1281_VD_RA0_RB(InstrData& i, StringBuffer* str);
void Disasm_VX1283_VD_VB(InstrData& i, StringBuffer* str);
void Disasm_VX1283_VD_VB_I(InstrData& i, StringBuffer* str);
void Disasm_VX_VD_VA_VB(InstrData& i, StringBuffer* str);
void Disasm_VX128_VD_VA_VB(InstrData& i, StringBuffer* str);
void Disasm_VX128_VD_VA_VD_VB(InstrData& i, StringBuffer* str);
void Disasm_VX1282_VD_VA_VB_VC(InstrData& i, StringBuffer* str);
void Disasm_VXA_VD_VA_VB_VC(InstrData& i, StringBuffer* str);
void Disasm_0(InstrData* i, StringBuffer* str);
void Disasm__(InstrData* i, StringBuffer* str);
void Disasm_X_FRT_FRB(InstrData* i, StringBuffer* str);
void Disasm_A_FRT_FRB(InstrData* i, StringBuffer* str);
void Disasm_A_FRT_FRA_FRB(InstrData* i, StringBuffer* str);
void Disasm_A_FRT_FRA_FRB_FRC(InstrData* i, StringBuffer* str);
void Disasm_X_RT_RA_RB(InstrData* i, StringBuffer* str);
void Disasm_X_RT_RA0_RB(InstrData* i, StringBuffer* str);
void Disasm_X_FRT_RA_RB(InstrData* i, StringBuffer* str);
void Disasm_X_FRT_RA0_RB(InstrData* i, StringBuffer* str);
void Disasm_D_RT_RA_I(InstrData* i, StringBuffer* str);
void Disasm_D_RT_RA0_I(InstrData* i, StringBuffer* str);
void Disasm_D_FRT_RA_I(InstrData* i, StringBuffer* str);
void Disasm_D_FRT_RA0_I(InstrData* i, StringBuffer* str);
void Disasm_DS_RT_RA_I(InstrData* i, StringBuffer* str);
void Disasm_DS_RT_RA0_I(InstrData* i, StringBuffer* str);
void Disasm_D_RA(InstrData* i, StringBuffer* str);
void Disasm_X_RA_RB(InstrData* i, StringBuffer* str);
void Disasm_XO_RT_RA_RB(InstrData* i, StringBuffer* str);
void Disasm_XO_RT_RA(InstrData* i, StringBuffer* str);
void Disasm_X_RA_RT_RB(InstrData* i, StringBuffer* str);
void Disasm_D_RA_RT_I(InstrData* i, StringBuffer* str);
void Disasm_X_RA_RT(InstrData* i, StringBuffer* str);
void Disasm_X_VX_RA0_RB(InstrData* i, StringBuffer* str);
void Disasm_VX1281_VD_RA0_RB(InstrData* i, StringBuffer* str);
void Disasm_VX1283_VD_VB(InstrData* i, StringBuffer* str);
void Disasm_VX1283_VD_VB_I(InstrData* i, StringBuffer* str);
void Disasm_VX_VD_VA_VB(InstrData* i, StringBuffer* str);
void Disasm_VX128_VD_VA_VB(InstrData* i, StringBuffer* str);
void Disasm_VX128_VD_VA_VD_VB(InstrData* i, StringBuffer* str);
void Disasm_VX1282_VD_VA_VB_VC(InstrData* i, StringBuffer* str);
void Disasm_VXA_VD_VA_VB_VC(InstrData* i, StringBuffer* str);
void Disasm_sync(InstrData& i, StringBuffer* str);
void Disasm_dcbf(InstrData& i, StringBuffer* str);
void Disasm_dcbz(InstrData& i, StringBuffer* str);
void Disasm_fcmp(InstrData& i, StringBuffer* str);
void Disasm_sync(InstrData* i, StringBuffer* str);
void Disasm_dcbf(InstrData* i, StringBuffer* str);
void Disasm_dcbz(InstrData* i, StringBuffer* str);
void Disasm_fcmp(InstrData* i, StringBuffer* str);
void Disasm_bx(InstrData& i, StringBuffer* str);
void Disasm_bcx(InstrData& i, StringBuffer* str);
void Disasm_bcctrx(InstrData& i, StringBuffer* str);
void Disasm_bclrx(InstrData& i, StringBuffer* str);
void Disasm_bx(InstrData* i, StringBuffer* str);
void Disasm_bcx(InstrData* i, StringBuffer* str);
void Disasm_bcctrx(InstrData* i, StringBuffer* str);
void Disasm_bclrx(InstrData* i, StringBuffer* str);
void Disasm_mfcr(InstrData& i, StringBuffer* str);
void Disasm_mfspr(InstrData& i, StringBuffer* str);
void Disasm_mtspr(InstrData& i, StringBuffer* str);
void Disasm_mftb(InstrData& i, StringBuffer* str);
void Disasm_mfmsr(InstrData& i, StringBuffer* str);
void Disasm_mtmsr(InstrData& i, StringBuffer* str);
void Disasm_mfcr(InstrData* i, StringBuffer* str);
void Disasm_mfspr(InstrData* i, StringBuffer* str);
void Disasm_mtspr(InstrData* i, StringBuffer* str);
void Disasm_mftb(InstrData* i, StringBuffer* str);
void Disasm_mfmsr(InstrData* i, StringBuffer* str);
void Disasm_mtmsr(InstrData* i, StringBuffer* str);
void Disasm_cmp(InstrData& i, StringBuffer* str);
void Disasm_cmpi(InstrData& i, StringBuffer* str);
void Disasm_cmpli(InstrData& i, StringBuffer* str);
void Disasm_cmp(InstrData* i, StringBuffer* str);
void Disasm_cmpi(InstrData* i, StringBuffer* str);
void Disasm_cmpli(InstrData* i, StringBuffer* str);
void Disasm_rld(InstrData& i, StringBuffer* str);
void Disasm_rlwim(InstrData& i, StringBuffer* str);
void Disasm_rlwnmx(InstrData& i, StringBuffer* str);
void Disasm_srawix(InstrData& i, StringBuffer* str);
void Disasm_sradix(InstrData& i, StringBuffer* str);
void Disasm_rld(InstrData* i, StringBuffer* str);
void Disasm_rlwim(InstrData* i, StringBuffer* str);
void Disasm_rlwnmx(InstrData* i, StringBuffer* str);
void Disasm_srawix(InstrData* i, StringBuffer* str);
void Disasm_sradix(InstrData* i, StringBuffer* str);
void Disasm_vpermwi128(InstrData& i, StringBuffer* str);
void Disasm_vrfin128(InstrData& i, StringBuffer* str);
void Disasm_vrlimi128(InstrData& i, StringBuffer* str);
void Disasm_vsldoi128(InstrData& i, StringBuffer* str);
void Disasm_vspltb(InstrData& i, StringBuffer* str);
void Disasm_vsplth(InstrData& i, StringBuffer* str);
void Disasm_vspltw(InstrData& i, StringBuffer* str);
void Disasm_vspltisb(InstrData& i, StringBuffer* str);
void Disasm_vspltish(InstrData& i, StringBuffer* str);
void Disasm_vspltisw(InstrData& i, StringBuffer* str);
void Disasm_vpermwi128(InstrData* i, StringBuffer* str);
void Disasm_vrfin128(InstrData* i, StringBuffer* str);
void Disasm_vrlimi128(InstrData* i, StringBuffer* str);
void Disasm_vsldoi128(InstrData* i, StringBuffer* str);
void Disasm_vspltb(InstrData* i, StringBuffer* str);
void Disasm_vsplth(InstrData* i, StringBuffer* str);
void Disasm_vspltw(InstrData* i, StringBuffer* str);
void Disasm_vspltisb(InstrData* i, StringBuffer* str);
void Disasm_vspltish(InstrData* i, StringBuffer* str);
void Disasm_vspltisw(InstrData* i, StringBuffer* str);
namespace tables {
@@ -1097,4 +1097,4 @@ static InstrType instr_table_scan[] = {
} // namespace cpu
} // namespace xe
#endif // XENIA_FRONTEND_PPC_INSTR_TABLES_H_
#endif // XENIA_CPU_FRONTEND_PPC_INSTR_TABLES_H_

8
src/xenia/cpu/frontend/ppc_scanner.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_FRONTEND_PPC_SCANNER_H_
#define XENIA_FRONTEND_PPC_SCANNER_H_
#ifndef XENIA_CPU_FRONTEND_PPC_SCANNER_H_
#define XENIA_CPU_FRONTEND_PPC_SCANNER_H_
#include <vector>
@@ -28,7 +28,7 @@ struct BlockInfo {
class PPCScanner {
public:
PPCScanner(PPCFrontend* frontend);
explicit PPCScanner(PPCFrontend* frontend);
~PPCScanner();
bool Scan(GuestFunction* function, DebugInfo* debug_info);
@@ -45,4 +45,4 @@ class PPCScanner {
} // namespace cpu
} // namespace xe
#endif // XENIA_FRONTEND_PPC_SCANNER_H_
#endif // XENIA_CPU_FRONTEND_PPC_SCANNER_H_

7
src/xenia/cpu/frontend/ppc_translator.cc
View File

@@ -33,9 +33,6 @@ namespace xe {
namespace cpu {
namespace frontend {
// TODO(benvanik): remove when enums redefined.
using namespace xe::cpu;
using xe::cpu::backend::Backend;
using xe::cpu::compiler::Compiler;
namespace passes = xe::cpu::compiler::passes;
@@ -208,7 +205,7 @@ bool PPCTranslator::Translate(GuestFunction* function,
}
return true;
};
}
void PPCTranslator::DumpSource(GuestFunction* function,
StringBuffer* string_buffer) {
@@ -239,7 +236,7 @@ void PPCTranslator::DumpSource(GuestFunction* function,
}
string_buffer->AppendFormat("%.8X %.8X ", address, i.code);
DisasmPPC(i, string_buffer);
DisasmPPC(&i, string_buffer);
string_buffer->Append('\n');
}
}

8
src/xenia/cpu/frontend/ppc_translator.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_FRONTEND_PPC_TRANSLATOR_H_
#define XENIA_FRONTEND_PPC_TRANSLATOR_H_
#ifndef XENIA_CPU_FRONTEND_PPC_TRANSLATOR_H_
#define XENIA_CPU_FRONTEND_PPC_TRANSLATOR_H_
#include <memory>
@@ -27,7 +27,7 @@ class PPCScanner;
class PPCTranslator {
public:
PPCTranslator(PPCFrontend* frontend);
explicit PPCTranslator(PPCFrontend* frontend);
~PPCTranslator();
bool Translate(GuestFunction* function, uint32_t debug_info_flags);
@@ -48,4 +48,4 @@ class PPCTranslator {
} // namespace cpu
} // namespace xe
#endif // XENIA_FRONTEND_PPC_TRANSLATOR_H_
#endif // XENIA_CPU_FRONTEND_PPC_TRANSLATOR_H_

6
src/xenia/cpu/hir/block.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_HIR_BLOCK_H_
#define XENIA_HIR_BLOCK_H_
#ifndef XENIA_CPU_HIR_BLOCK_H_
#define XENIA_CPU_HIR_BLOCK_H_
#include "xenia/base/arena.h"
@@ -70,4 +70,4 @@ class Block {
} // namespace cpu
} // namespace xe
#endif // XENIA_HIR_BLOCK_H_
#endif // XENIA_CPU_HIR_BLOCK_H_

4
src/xenia/cpu/hir/hir_builder.cc
View File

@@ -21,7 +21,7 @@
#include "xenia/profiling.h"
// Will scribble arena memory to hopefully find use before clears.
//#define SCRIBBLE_ARENA_ON_RESET
// #define SCRIBBLE_ARENA_ON_RESET
namespace xe {
namespace cpu {
@@ -243,7 +243,7 @@ void HIRBuilder::Dump(StringBuffer* str) {
continue;
}
if (i->opcode == &OPCODE_COMMENT_info) {
str->AppendFormat(" ; %s\n", (char*)i->src1.offset);
str->AppendFormat(" ; %s\n", reinterpret_cast<char*>(i->src1.offset));
i = i->next;
continue;
}

6
src/xenia/cpu/hir/hir_builder.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_HIR_HIR_BUILDER_H_
#define XENIA_HIR_HIR_BUILDER_H_
#ifndef XENIA_CPU_HIR_HIR_BUILDER_H_
#define XENIA_CPU_HIR_HIR_BUILDER_H_
#include <vector>
@@ -272,4 +272,4 @@ class HIRBuilder {
} // namespace cpu
} // namespace xe
#endif // XENIA_HIR_HIR_BUILDER_H_
#endif // XENIA_CPU_HIR_HIR_BUILDER_H_

6
src/xenia/cpu/hir/instr.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_HIR_INSTR_H_
#define XENIA_HIR_INSTR_H_
#ifndef XENIA_CPU_HIR_INSTR_H_
#define XENIA_CPU_HIR_INSTR_H_
#include "xenia/cpu/hir/opcodes.h"
#include "xenia/cpu/hir/value.h"
@@ -65,4 +65,4 @@ class Instr {
} // namespace cpu
} // namespace xe
#endif // XENIA_HIR_INSTR_H_
#endif // XENIA_CPU_HIR_INSTR_H_

6
src/xenia/cpu/hir/label.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_HIR_LABEL_H_
#define XENIA_HIR_LABEL_H_
#ifndef XENIA_CPU_HIR_LABEL_H_
#define XENIA_CPU_HIR_LABEL_H_
namespace xe {
namespace cpu {
@@ -32,4 +32,4 @@ class Label {
} // namespace cpu
} // namespace xe
#endif // XENIA_HIR_LABEL_H_
#endif // XENIA_CPU_HIR_LABEL_H_

2
src/xenia/cpu/hir/opcodes.cc
View File

@@ -9,8 +9,6 @@
#include "xenia/cpu/hir/opcodes.h"
using namespace xe::cpu::hir;
namespace xe {
namespace cpu {
namespace hir {

45
src/xenia/cpu/hir/opcodes.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_HIR_OPCODES_H_
#define XENIA_HIR_OPCODES_H_
#ifndef XENIA_CPU_HIR_OPCODES_H_
#define XENIA_CPU_HIR_OPCODES_H_
#include <cstdint>
@@ -20,10 +20,12 @@ enum CallFlags {
CALL_TAIL = (1 << 1),
CALL_POSSIBLE_RETURN = (1 << 2),
};
enum BranchFlags {
BRANCH_LIKELY = (1 << 1),
BRANCH_UNLIKELY = (1 << 2),
};
enum RoundMode {
// to zero/nearest/etc
ROUND_TO_ZERO = 0,
@@ -31,31 +33,45 @@ enum RoundMode {
ROUND_TO_MINUS_INFINITY,
ROUND_TO_POSITIVE_INFINITY,
};
enum LoadStoreFlags {
LOAD_STORE_BYTE_SWAP = 1 << 0,
};
enum PrefetchFlags {
PREFETCH_LOAD = (1 << 1),
PREFETCH_STORE = (1 << 2),
};
enum ArithmeticFlags {
ARITHMETIC_UNSIGNED = (1 << 2),
ARITHMETIC_SATURATE = (1 << 3),
};
#define PERMUTE_MASK(sel_x, x, sel_y, y, sel_z, z, sel_w, w) \
((((x)&0x3) << 0) | (sel_x << 2) | (((y)&0x3) << 8) | (sel_y << 10) | \
(((z)&0x3) << 16) | (sel_z << 18) | (((w)&0x3) << 24) | (sel_w << 26))
enum Permutes {
PERMUTE_IDENTITY = PERMUTE_MASK(0, 0, 0, 1, 0, 2, 0, 3),
constexpr uint32_t MakePermuteMask(uint32_t sel_x, uint32_t x, uint32_t sel_y,
uint32_t y, uint32_t sel_z, uint32_t z,
uint32_t sel_w, uint32_t w) {
return ((x & 0x3) << 0) | (sel_x << 2) | ((y & 0x3) << 8) | (sel_y << 10) |
((z & 0x3) << 16) | (sel_z << 18) | ((w & 0x3) << 24) | (sel_w << 26);
}
enum PermuteMasks : uint32_t {
kIdentityPermuteMask = MakePermuteMask(0, 0, 0, 1, 0, 2, 0, 3),
};
#define SWIZZLE_MASK(x, y, z, w) \
((((x)&0x3) << 0) | (((y)&0x3) << 2) | (((z)&0x3) << 4) | (((w)&0x3) << 6))
constexpr uint32_t MakeSwizzleMask(uint32_t x, uint32_t y, uint32_t z,
uint32_t w) {
return ((x & 0x3) << 0) | ((y & 0x3) << 2) | ((z & 0x3) << 4) |
((w & 0x3) << 6);
}
enum Swizzles {
SWIZZLE_XYZW_TO_XYZW = SWIZZLE_MASK(0, 1, 2, 3),
SWIZZLE_XYZW_TO_YZWX = SWIZZLE_MASK(1, 2, 3, 0),
SWIZZLE_XYZW_TO_ZWXY = SWIZZLE_MASK(2, 3, 0, 1),
SWIZZLE_XYZW_TO_WXYZ = SWIZZLE_MASK(3, 0, 1, 2),
SWIZZLE_XYZW_TO_XYZW = MakeSwizzleMask(0, 1, 2, 3),
SWIZZLE_XYZW_TO_YZWX = MakeSwizzleMask(1, 2, 3, 0),
SWIZZLE_XYZW_TO_ZWXY = MakeSwizzleMask(2, 3, 0, 1),
SWIZZLE_XYZW_TO_WXYZ = MakeSwizzleMask(3, 0, 1, 2),
};
enum PackType : uint16_t {
// Special types:
PACK_TYPE_D3DCOLOR = 0,
@@ -82,6 +98,7 @@ enum PackType : uint16_t {
PACK_TYPE_OUT_UNSATURATE = 0 << 15,
PACK_TYPE_OUT_SATURATE = 1 << 15,
};
inline bool IsPackToHi(uint32_t flags) {
return (flags & PACK_TYPE_TO_HI) == PACK_TYPE_TO_HI;
}
@@ -284,4 +301,4 @@ typedef struct {
} // namespace cpu
} // namespace xe
#endif // XENIA_HIR_OPCODES_H_
#endif // XENIA_CPU_HIR_OPCODES_H_

14
src/xenia/cpu/hir/value.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_HIR_VALUE_H_
#define XENIA_HIR_VALUE_H_
#ifndef XENIA_CPU_HIR_VALUE_H_
#define XENIA_CPU_HIR_VALUE_H_
#include "xenia/base/arena.h"
#include "xenia/base/assert.h"
@@ -105,14 +105,6 @@ class Value {
Use* AddUse(Arena* arena, Instr* instr);
void RemoveUse(Use* use);
int8_t get_constant(int8_t) const { return constant.i8; }
int16_t get_constant(int16_t) const { return constant.i16; }
int32_t get_constant(int32_t) const { return constant.i32; }
int64_t get_constant(int64_t) const { return constant.i64; }
float get_constant(float) const { return constant.f32; }
double get_constant(double) const { return constant.f64; }
vec128_t get_constant(vec128_t&) const { return constant.v128; }
void set_zero(TypeName new_type) {
type = new_type;
flags |= VALUE_IS_CONSTANT;
@@ -511,4 +503,4 @@ class Value {
} // namespace cpu
} // namespace xe
#endif // XENIA_HIR_VALUE_H_
#endif // XENIA_CPU_HIR_VALUE_H_

8
src/xenia/cpu/testing/permute_test.cc
View File

@@ -17,7 +17,7 @@ using xe::cpu::frontend::PPCContext;
TEST_CASE("PERMUTE_V128_BY_INT32_CONSTANT", "[instr]") {
{
uint32_t mask = PERMUTE_MASK(0, 0, 0, 1, 0, 2, 0, 3);
uint32_t mask = MakePermuteMask(0, 0, 0, 1, 0, 2, 0, 3);
TestFunction([mask](HIRBuilder& b) {
StoreVR(b, 3, b.Permute(b.LoadConstantUint32(mask), LoadVR(b, 4),
LoadVR(b, 5), INT32_TYPE));
@@ -34,7 +34,7 @@ TEST_CASE("PERMUTE_V128_BY_INT32_CONSTANT", "[instr]") {
});
}
{
uint32_t mask = PERMUTE_MASK(1, 0, 1, 1, 1, 2, 1, 3);
uint32_t mask = MakePermuteMask(1, 0, 1, 1, 1, 2, 1, 3);
TestFunction([mask](HIRBuilder& b) {
StoreVR(b, 3, b.Permute(b.LoadConstantUint32(mask), LoadVR(b, 4),
LoadVR(b, 5), INT32_TYPE));
@@ -51,7 +51,7 @@ TEST_CASE("PERMUTE_V128_BY_INT32_CONSTANT", "[instr]") {
});
}
{
uint32_t mask = PERMUTE_MASK(0, 3, 0, 2, 0, 1, 0, 0);
uint32_t mask = MakePermuteMask(0, 3, 0, 2, 0, 1, 0, 0);
TestFunction([mask](HIRBuilder& b) {
StoreVR(b, 3, b.Permute(b.LoadConstantUint32(mask), LoadVR(b, 4),
LoadVR(b, 5), INT32_TYPE));
@@ -68,7 +68,7 @@ TEST_CASE("PERMUTE_V128_BY_INT32_CONSTANT", "[instr]") {
});
}
{
uint32_t mask = PERMUTE_MASK(1, 3, 1, 2, 1, 1, 1, 0);
uint32_t mask = MakePermuteMask(1, 3, 1, 2, 1, 1, 1, 0);
TestFunction([mask](HIRBuilder& b) {
StoreVR(b, 3, b.Permute(b.LoadConstantUint32(mask), LoadVR(b, 4),
LoadVR(b, 5), INT32_TYPE));

6
src/xenia/cpu/testing/swizzle_test.cc
View File

@@ -18,7 +18,7 @@ using xe::cpu::frontend::PPCContext;
TEST_CASE("SWIZZLE_V128", "[instr]") {
TestFunction([](HIRBuilder& b) {
StoreVR(b, 3,
b.Swizzle(LoadVR(b, 4), INT32_TYPE, SWIZZLE_MASK(0, 1, 2, 3)));
b.Swizzle(LoadVR(b, 4), INT32_TYPE, MakeSwizzleMask(0, 1, 2, 3)));
b.Return();
})
.Run([](PPCContext* ctx) { ctx->v[4] = vec128i(0, 1, 2, 3); },
@@ -28,7 +28,7 @@ TEST_CASE("SWIZZLE_V128", "[instr]") {
});
TestFunction([](HIRBuilder& b) {
StoreVR(b, 3,
b.Swizzle(LoadVR(b, 4), INT32_TYPE, SWIZZLE_MASK(3, 2, 1, 0)));
b.Swizzle(LoadVR(b, 4), INT32_TYPE, MakeSwizzleMask(3, 2, 1, 0)));
b.Return();
})
.Run([](PPCContext* ctx) { ctx->v[4] = vec128i(0, 1, 2, 3); },
@@ -38,7 +38,7 @@ TEST_CASE("SWIZZLE_V128", "[instr]") {
});
TestFunction([](HIRBuilder& b) {
StoreVR(b, 3,
b.Swizzle(LoadVR(b, 4), INT32_TYPE, SWIZZLE_MASK(1, 1, 2, 2)));
b.Swizzle(LoadVR(b, 4), INT32_TYPE, MakeSwizzleMask(1, 1, 2, 2)));
b.Return();
})
.Run([](PPCContext* ctx) { ctx->v[4] = vec128i(0, 1, 2, 3); },

8
src/xenia/cpu/testing/util.h
View File

@@ -7,8 +7,10 @@
******************************************************************************
*/
#ifndef XENIA_TESTING_UTIL_H_
#define XENIA_TESTING_UTIL_H_
#ifndef XENIA_CPU_TESTING_UTIL_H_
#define XENIA_CPU_TESTING_UTIL_H_
#include <vector>
#include "xenia/base/main.h"
#include "xenia/cpu/backend/x64/x64_backend.h"
@@ -114,4 +116,4 @@ inline void StoreVR(hir::HIRBuilder& b, int reg, hir::Value* value) {
} // namespace cpu
} // namespace xe
#endif // XENIA_TESTING_UTIL_H_
#endif // XENIA_CPU_TESTING_UTIL_H_

3
src/xenia/cpu/xex_module.cc
View File

@@ -56,7 +56,8 @@ bool XexModule::GetOptHeader(const xex2_header* header, xe_xex2_header_keys key,
} break;
case 0x01: {
// Pointer to the value on the optional header.
*out_ptr = (void*)&opt_header.value;
*out_ptr = const_cast<void*>(
reinterpret_cast<const void*>(&opt_header.value));
} break;
default: {
// Pointer to the header.