More style.

src/xenia/cpu/compiler/passes/context_promotion_pass.h

@@ -11,6 +11,7 @@
 #define XENIA_CPU_COMPILER_PASSES_CONTEXT_PROMOTION_PASS_H_
 
 #include <cmath>
+#include <vector>
 
 #include "xenia/base/platform.h"
 #include "xenia/cpu/compiler/compiler_pass.h"

src/xenia/cpu/compiler/passes/data_flow_analysis_pass.cc

@@ -71,8 +71,8 @@ void DataFlowAnalysisPass::AnalyzeFlow(HIRBuilder* builder,
 
   // Stash for value map. We may want to maintain this during building.
   auto arena = builder->arena();
-  Value** value_map =
-      (Value**)arena->Alloc(sizeof(Value*) * max_value_estimate);
+  auto value_map = reinterpret_cast<Value**>(
+      arena->Alloc(sizeof(Value*) * max_value_estimate));
 
   // Allocate incoming bitvectors for use by blocks. We don't need outgoing
   // because they are only used during the block iteration.

src/xenia/cpu/compiler/passes/finalization_pass.cc

@@ -44,7 +44,7 @@ bool FinalizationPass::Run(HIRBuilder* builder) {
     while (label) {
       if (!label->name) {
         const size_t label_len = 6 + 4 + 1;
-        char* name = (char*)arena->Alloc(label_len);
+        char* name = reinterpret_cast<char*>(arena->Alloc(label_len));
         snprintf(name, label_len, "_label%d", label->id);
         label->name = name;
       }

src/xenia/cpu/compiler/passes/register_allocation_pass.cc

@@ -180,7 +180,8 @@ void RegisterAllocationPass::DumpUsage(const char* name) {
     auto usage_set = usage_sets_.all_sets[i];
     if (usage_set) {
       fprintf(stdout, "set %s:\n", usage_set->set->name);
-      fprintf(stdout, "  avail: %s\n", usage_set->availability.to_string().c_str());
+      fprintf(stdout, "  avail: %s\n",
+              usage_set->availability.to_string().c_str());
       fprintf(stdout, "  upcoming uses:\n");
       for (auto it = usage_set->upcoming_uses.begin();
            it != usage_set->upcoming_uses.end(); ++it) {

src/xenia/cpu/compiler/passes/register_allocation_pass.h

@@ -12,6 +12,7 @@
 
 #include <algorithm>
 #include <bitset>
+#include <functional>
 #include <vector>
 
 #include "xenia/cpu/backend/machine_info.h"
@@ -24,7 +25,7 @@ namespace passes {
 
 class RegisterAllocationPass : public CompilerPass {
  public:
-  RegisterAllocationPass(const backend::MachineInfo* machine_info);
+  explicit RegisterAllocationPass(const backend::MachineInfo* machine_info);
   ~RegisterAllocationPass() override;
 
   bool Run(hir::HIRBuilder* builder) override;

src/xenia/cpu/compiler/passes/validation_pass.cc

@@ -37,7 +37,7 @@ bool ValidationPass::Run(HIRBuilder* builder) {
 #if 0
   StringBuffer str;
   builder->Dump(&str);
-  printf(str.GetString());
+  printf("%s", str.GetString());
   fflush(stdout);
   str.Reset();
 #endif  // 0

src/xenia/cpu/compiler/passes/value_reduction_pass.cc

@@ -79,10 +79,10 @@ bool ValueReductionPass::Run(HIRBuilder* builder) {
     instr = block->instr_head;
     while (instr) {
       const OpcodeInfo* info = instr->opcode;
-      OpcodeSignatureType dest_type = GET_OPCODE_SIG_TYPE_DEST(info->signature);
-      OpcodeSignatureType src1_type = GET_OPCODE_SIG_TYPE_SRC1(info->signature);
-      OpcodeSignatureType src2_type = GET_OPCODE_SIG_TYPE_SRC2(info->signature);
-      OpcodeSignatureType src3_type = GET_OPCODE_SIG_TYPE_SRC3(info->signature);
+      auto dest_type = GET_OPCODE_SIG_TYPE_DEST(info->signature);
+      auto src1_type = GET_OPCODE_SIG_TYPE_SRC1(info->signature);
+      auto src2_type = GET_OPCODE_SIG_TYPE_SRC2(info->signature);
+      auto src3_type = GET_OPCODE_SIG_TYPE_SRC3(info->signature);
       if (src1_type == OPCODE_SIG_TYPE_V) {
         auto v = instr->src1.value;
         if (!v->last_use) {