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More style.

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This commit is contained in:
Ben Vanik
2015-08-07 21:29:03 -07:00
parent 14beb27ebc
commit a92566dfc5
131 changed files with 1141 additions and 1056 deletions
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6
src/xenia/cpu/hir/block.h
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@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_HIR_BLOCK_H_
#define XENIA_HIR_BLOCK_H_
#ifndef XENIA_CPU_HIR_BLOCK_H_
#define XENIA_CPU_HIR_BLOCK_H_
#include "xenia/base/arena.h"
@@ -70,4 +70,4 @@ class Block {
} // namespace cpu
} // namespace xe
#endif // XENIA_HIR_BLOCK_H_
#endif // XENIA_CPU_HIR_BLOCK_H_

4
src/xenia/cpu/hir/hir_builder.cc
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@@ -21,7 +21,7 @@
#include "xenia/profiling.h"
// Will scribble arena memory to hopefully find use before clears.
//#define SCRIBBLE_ARENA_ON_RESET
// #define SCRIBBLE_ARENA_ON_RESET
namespace xe {
namespace cpu {
@@ -243,7 +243,7 @@ void HIRBuilder::Dump(StringBuffer* str) {
continue;
}
if (i->opcode == &OPCODE_COMMENT_info) {
str->AppendFormat(" ; %s\n", (char*)i->src1.offset);
str->AppendFormat(" ; %s\n", reinterpret_cast<char*>(i->src1.offset));
i = i->next;
continue;
}

6
src/xenia/cpu/hir/hir_builder.h
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@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_HIR_HIR_BUILDER_H_
#define XENIA_HIR_HIR_BUILDER_H_
#ifndef XENIA_CPU_HIR_HIR_BUILDER_H_
#define XENIA_CPU_HIR_HIR_BUILDER_H_
#include <vector>
@@ -272,4 +272,4 @@ class HIRBuilder {
} // namespace cpu
} // namespace xe
#endif // XENIA_HIR_HIR_BUILDER_H_
#endif // XENIA_CPU_HIR_HIR_BUILDER_H_

6
src/xenia/cpu/hir/instr.h
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@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_HIR_INSTR_H_
#define XENIA_HIR_INSTR_H_
#ifndef XENIA_CPU_HIR_INSTR_H_
#define XENIA_CPU_HIR_INSTR_H_
#include "xenia/cpu/hir/opcodes.h"
#include "xenia/cpu/hir/value.h"
@@ -65,4 +65,4 @@ class Instr {
} // namespace cpu
} // namespace xe
#endif // XENIA_HIR_INSTR_H_
#endif // XENIA_CPU_HIR_INSTR_H_

6
src/xenia/cpu/hir/label.h
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@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_HIR_LABEL_H_
#define XENIA_HIR_LABEL_H_
#ifndef XENIA_CPU_HIR_LABEL_H_
#define XENIA_CPU_HIR_LABEL_H_
namespace xe {
namespace cpu {
@@ -32,4 +32,4 @@ class Label {
} // namespace cpu
} // namespace xe
#endif // XENIA_HIR_LABEL_H_
#endif // XENIA_CPU_HIR_LABEL_H_

2
src/xenia/cpu/hir/opcodes.cc
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@@ -9,8 +9,6 @@
#include "xenia/cpu/hir/opcodes.h"
using namespace xe::cpu::hir;
namespace xe {
namespace cpu {
namespace hir {

45
src/xenia/cpu/hir/opcodes.h
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@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_HIR_OPCODES_H_
#define XENIA_HIR_OPCODES_H_
#ifndef XENIA_CPU_HIR_OPCODES_H_
#define XENIA_CPU_HIR_OPCODES_H_
#include <cstdint>
@@ -20,10 +20,12 @@ enum CallFlags {
CALL_TAIL = (1 << 1),
CALL_POSSIBLE_RETURN = (1 << 2),
};
enum BranchFlags {
BRANCH_LIKELY = (1 << 1),
BRANCH_UNLIKELY = (1 << 2),
};
enum RoundMode {
// to zero/nearest/etc
ROUND_TO_ZERO = 0,
@@ -31,31 +33,45 @@ enum RoundMode {
ROUND_TO_MINUS_INFINITY,
ROUND_TO_POSITIVE_INFINITY,
};
enum LoadStoreFlags {
LOAD_STORE_BYTE_SWAP = 1 << 0,
};
enum PrefetchFlags {
PREFETCH_LOAD = (1 << 1),
PREFETCH_STORE = (1 << 2),
};
enum ArithmeticFlags {
ARITHMETIC_UNSIGNED = (1 << 2),
ARITHMETIC_SATURATE = (1 << 3),
};
#define PERMUTE_MASK(sel_x, x, sel_y, y, sel_z, z, sel_w, w) \
((((x)&0x3) << 0) | (sel_x << 2) | (((y)&0x3) << 8) | (sel_y << 10) | \
(((z)&0x3) << 16) | (sel_z << 18) | (((w)&0x3) << 24) | (sel_w << 26))
enum Permutes {
PERMUTE_IDENTITY = PERMUTE_MASK(0, 0, 0, 1, 0, 2, 0, 3),
constexpr uint32_t MakePermuteMask(uint32_t sel_x, uint32_t x, uint32_t sel_y,
uint32_t y, uint32_t sel_z, uint32_t z,
uint32_t sel_w, uint32_t w) {
return ((x & 0x3) << 0) | (sel_x << 2) | ((y & 0x3) << 8) | (sel_y << 10) |
((z & 0x3) << 16) | (sel_z << 18) | ((w & 0x3) << 24) | (sel_w << 26);
}
enum PermuteMasks : uint32_t {
kIdentityPermuteMask = MakePermuteMask(0, 0, 0, 1, 0, 2, 0, 3),
};
#define SWIZZLE_MASK(x, y, z, w) \
((((x)&0x3) << 0) | (((y)&0x3) << 2) | (((z)&0x3) << 4) | (((w)&0x3) << 6))
constexpr uint32_t MakeSwizzleMask(uint32_t x, uint32_t y, uint32_t z,
uint32_t w) {
return ((x & 0x3) << 0) | ((y & 0x3) << 2) | ((z & 0x3) << 4) |
((w & 0x3) << 6);
}
enum Swizzles {
SWIZZLE_XYZW_TO_XYZW = SWIZZLE_MASK(0, 1, 2, 3),
SWIZZLE_XYZW_TO_YZWX = SWIZZLE_MASK(1, 2, 3, 0),
SWIZZLE_XYZW_TO_ZWXY = SWIZZLE_MASK(2, 3, 0, 1),
SWIZZLE_XYZW_TO_WXYZ = SWIZZLE_MASK(3, 0, 1, 2),
SWIZZLE_XYZW_TO_XYZW = MakeSwizzleMask(0, 1, 2, 3),
SWIZZLE_XYZW_TO_YZWX = MakeSwizzleMask(1, 2, 3, 0),
SWIZZLE_XYZW_TO_ZWXY = MakeSwizzleMask(2, 3, 0, 1),
SWIZZLE_XYZW_TO_WXYZ = MakeSwizzleMask(3, 0, 1, 2),
};
enum PackType : uint16_t {
// Special types:
PACK_TYPE_D3DCOLOR = 0,
@@ -82,6 +98,7 @@ enum PackType : uint16_t {
PACK_TYPE_OUT_UNSATURATE = 0 << 15,
PACK_TYPE_OUT_SATURATE = 1 << 15,
};
inline bool IsPackToHi(uint32_t flags) {
return (flags & PACK_TYPE_TO_HI) == PACK_TYPE_TO_HI;
}
@@ -284,4 +301,4 @@ typedef struct {
} // namespace cpu
} // namespace xe
#endif // XENIA_HIR_OPCODES_H_
#endif // XENIA_CPU_HIR_OPCODES_H_

14
src/xenia/cpu/hir/value.h
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@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_HIR_VALUE_H_
#define XENIA_HIR_VALUE_H_
#ifndef XENIA_CPU_HIR_VALUE_H_
#define XENIA_CPU_HIR_VALUE_H_
#include "xenia/base/arena.h"
#include "xenia/base/assert.h"
@@ -105,14 +105,6 @@ class Value {
Use* AddUse(Arena* arena, Instr* instr);
void RemoveUse(Use* use);
int8_t get_constant(int8_t) const { return constant.i8; }
int16_t get_constant(int16_t) const { return constant.i16; }
int32_t get_constant(int32_t) const { return constant.i32; }
int64_t get_constant(int64_t) const { return constant.i64; }
float get_constant(float) const { return constant.f32; }
double get_constant(double) const { return constant.f64; }
vec128_t get_constant(vec128_t&) const { return constant.v128; }
void set_zero(TypeName new_type) {
type = new_type;
flags |= VALUE_IS_CONSTANT;
@@ -511,4 +503,4 @@ class Value {
} // namespace cpu
} // namespace xe
#endif // XENIA_HIR_VALUE_H_
#endif // XENIA_CPU_HIR_VALUE_H_