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[GPU] Remove most hardcoded register/instruction layouts from common and D3D12 code

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Triang3l
2019-10-20 19:40:37 +03:00
parent f83269cf8c
commit a9ed73bdd1
24 changed files with 896 additions and 942 deletions
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20
src/xenia/gpu/d3d12/pipeline_cache.h
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@@ -152,21 +152,21 @@ class PipelineCache {
uint32_t depth_clip : 1; // 15
uint32_t rov_msaa : 1; // 16
DepthRenderTargetFormat depth_format : 1; // 17
uint32_t depth_func : 3; // 20
CompareFunction depth_func : 3; // 20
uint32_t depth_write : 1; // 21
uint32_t stencil_enable : 1; // 22
uint32_t stencil_read_mask : 8; // 30
uint32_t force_early_z : 1; // 31
uint32_t stencil_write_mask : 8; // 8
uint32_t stencil_front_fail_op : 3; // 11
uint32_t stencil_front_depth_fail_op : 3; // 14
uint32_t stencil_front_pass_op : 3; // 17
uint32_t stencil_front_func : 3; // 20
uint32_t stencil_back_fail_op : 3; // 23
uint32_t stencil_back_depth_fail_op : 3; // 26
uint32_t stencil_back_pass_op : 3; // 29
uint32_t stencil_back_func : 3; // 32
uint32_t stencil_write_mask : 8; // 8
StencilOp stencil_front_fail_op : 3; // 11
StencilOp stencil_front_depth_fail_op : 3; // 14
StencilOp stencil_front_pass_op : 3; // 17
CompareFunction stencil_front_func : 3; // 20
StencilOp stencil_back_fail_op : 3; // 23
StencilOp stencil_back_depth_fail_op : 3; // 26
StencilOp stencil_back_pass_op : 3; // 29
CompareFunction stencil_back_func : 3; // 32
PipelineRenderTarget render_targets[4];
};