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bool-ifying xe::cpu

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This commit is contained in:
Ben Vanik
2015-05-05 17:21:08 -07:00
parent a38b05db24
commit ade5388728
67 changed files with 270 additions and 347 deletions
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6
src/xenia/cpu/frontend/ppc_scanner.cc
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@@ -35,13 +35,13 @@ PPCScanner::~PPCScanner() {}
bool PPCScanner::IsRestGprLr(uint32_t address) {
FunctionInfo* symbol_info;
if (frontend_->processor()->LookupFunctionInfo(address, &symbol_info)) {
if (!frontend_->processor()->LookupFunctionInfo(address, &symbol_info)) {
return false;
}
return symbol_info->behavior() == FunctionInfo::BEHAVIOR_EPILOG_RETURN;
}
int PPCScanner::FindExtents(FunctionInfo* symbol_info) {
bool PPCScanner::Scan(FunctionInfo* symbol_info, DebugInfo* debug_info) {
// This is a simple basic block analyizer. It walks the start address to the
// end address looking for branches. Each span of instructions between
// branches is considered a basic block. When the last blr (that has no
@@ -275,7 +275,7 @@ int PPCScanner::FindExtents(FunctionInfo* symbol_info) {
// - record prolog/epilog lengths/stack size/etc
LOGPPC("Finished analyzing %.8X", start_address);
return 0;
return true;
}
std::vector<BlockInfo> PPCScanner::FindBlocks(FunctionInfo* symbol_info) {