[Testing] Add more tests for logic, conversion and fp instructions
This commit is contained in:
Herman S.
34
src/xenia/cpu/ppc/testing/instr_vcfux.s
Normal file
34
src/xenia/cpu/ppc/testing/instr_vcfux.s
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@@ -0,0 +1,34 @@
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test_vcfux_1:
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#_ REGISTER_IN v4 [00000001, 00000002, 00000003, 00000004]
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vcfux v5, v4, 0
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blr
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#_ REGISTER_OUT v4 [00000001, 00000002, 00000003, 00000004]
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#_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000]
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test_vcfux_2:
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vcfux v5, v4, 0
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blr
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vcfux_3:
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#_ REGISTER_IN v4 [00000008, 00000010, 00000020, 00000040]
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vcfux v5, v4, 1
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blr
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#_ REGISTER_OUT v4 [00000008, 00000010, 00000020, 00000040]
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#_ REGISTER_OUT v5 [40800000, 41000000, 41800000, 42000000]
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test_vcfux_4:
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#_ REGISTER_IN v4 [00000100, 00000200, 00000400, 00000800]
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vcfux v5, v4, 4
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blr
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#_ REGISTER_OUT v4 [00000100, 00000200, 00000400, 00000800]
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#_ REGISTER_OUT v5 [41800000, 42000000, 42800000, 43000000]
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test_vcfux_5:
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#_ REGISTER_IN v4 [000000FF, 000001FF, 000003FF, 000007FF]
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vcfux v5, v4, 0
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blr
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#_ REGISTER_OUT v4 [000000FF, 000001FF, 000003FF, 000007FF]
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#_ REGISTER_OUT v5 [437F0000, 43FF8000, 447FC000, 44FFE000]
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54
src/xenia/cpu/ppc/testing/instr_vnmsubfp.s
Normal file
54
src/xenia/cpu/ppc/testing/instr_vnmsubfp.s
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@@ -0,0 +1,54 @@
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test_vnmsubfp_1:
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#_ REGISTER_IN v3 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_IN v5 [40000000, 40000000, 40000000, 40000000]
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vnmsubfp v6, v3, v5, v4
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blr
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#_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_OUT v5 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_OUT v6 [C0400000, C0400000, C0400000, C0400000]
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test_vnmsubfp_2:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_IN v5 [40000000, 40400000, 40800000, 40A00000]
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vnmsubfp v6, v3, v5, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_OUT v5 [40000000, 40400000, 40800000, 40A00000]
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#_ REGISTER_OUT v6 [3F800000, 40000000, 40400000, 40800000]
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test_vnmsubfp_3:
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#_ REGISTER_IN v3 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v5 [40000000, 40000000, 40000000, 40000000]
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vnmsubfp v6, v3, v5, v4
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blr
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#_ REGISTER_OUT v3 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_OUT v6 [C0000000, C0800000, C0C00000, C1000000]
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test_vnmsubfp_4:
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#_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_IN v5 [3F800000, 3F800000, 3F800000, 3F800000]
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vnmsubfp v6, v3, v5, v4
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blr
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#_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_OUT v5 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_OUT v6 [80000000, 80000000, 80000000, 80000000]
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test_vnmsubfp_5:
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#_ REGISTER_IN v3 [40400000, 40400000, 40400000, 40400000]
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#_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_IN v5 [40000000, 40000000, 40000000, 40000000]
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vnmsubfp v6, v3, v5, v4
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blr
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#_ REGISTER_OUT v3 [40400000, 40400000, 40400000, 40400000]
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#_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_OUT v5 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_OUT v6 [C0A00000, C0A00000, C0A00000, C0A00000]
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44
src/xenia/cpu/ppc/testing/instr_vnor.s
Normal file
44
src/xenia/cpu/ppc/testing/instr_vnor.s
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@@ -0,0 +1,44 @@
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test_vnor_1:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vnor v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vnor_2:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vnor v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vnor_3:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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vnor v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vnor_4:
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#_ REGISTER_IN v3 [F0F0F0F0, F0F0F0F0, F0F0F0F0, F0F0F0F0]
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#_ REGISTER_IN v4 [0F0F0F0F, 0F0F0F0F, 0F0F0F0F, 0F0F0F0F]
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vnor v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [F0F0F0F0, F0F0F0F0, F0F0F0F0, F0F0F0F0]
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#_ REGISTER_OUT v4 [0F0F0F0F, 0F0F0F0F, 0F0F0F0F, 0F0F0F0F]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vnor_5:
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#_ REGISTER_IN v3 [AAAAAAAA, 55555555, CCCCCCCC, 33333333]
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#_ REGISTER_IN v4 [55555555, AAAAAAAA, 33333333, CCCCCCCC]
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vnor v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [AAAAAAAA, 55555555, CCCCCCCC, 33333333]
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#_ REGISTER_OUT v4 [55555555, AAAAAAAA, 33333333, CCCCCCCC]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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34
src/xenia/cpu/ppc/testing/instr_vrefp.s
Normal file
34
src/xenia/cpu/ppc/testing/instr_vrefp.s
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@@ -0,0 +1,34 @@
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test_vrefp_1:
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#_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000]
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vrefp v5, v4
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blr
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#_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_OUT v5 [3F800000, 3F000000, 3EAAAAAB, 3E800000]
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test_vrefp_2:
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#_ REGISTER_IN v4 [40A00000, 40C00000, 40E00000, 41000000]
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vrefp v5, v4
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blr
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#_ REGISTER_OUT v4 [40A00000, 40C00000, 40E00000, 41000000]
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#_ REGISTER_OUT v5 [3E4CCCCD, 3E2AAAAB, 3E124925, 3E000000]
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test_vrefp_3:
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#_ REGISTER_IN v4 [3F000000, 3E800000, 3E000000, 3D800000]
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vrefp v5, v4
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blr
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#_ REGISTER_OUT v4 [3F000000, 3E800000, 3E000000, 3D800000]
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#_ REGISTER_OUT v5 [40000000, 40800000, 41000000, 41800000]
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test_vrefp_4:
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#_ REGISTER_IN v4 [BF800000, C0000000, C0400000, C0800000]
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vrefp v5, v4
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blr
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#_ REGISTER_OUT v4 [BF800000, C0000000, C0400000, C0800000]
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#_ REGISTER_OUT v5 [BF800000, BF000000, BEAAAAAB, BE800000]
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test_vrefp_5:
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#_ REGISTER_IN v4 [42C80000, 43480000, 43960000, 44160000]
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vrefp v5, v4
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blr
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#_ REGISTER_OUT v4 [42C80000, 43480000, 43960000, 44160000]
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#_ REGISTER_OUT v5 [3C23D70A, 3BA3D70A, 3B5A740E, 3ADA740E]
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34
src/xenia/cpu/ppc/testing/instr_vrfim.s
Normal file
34
src/xenia/cpu/ppc/testing/instr_vrfim.s
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@@ -0,0 +1,34 @@
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test_vrfim_1:
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#_ REGISTER_IN v4 [3FC00000, 40100000, 40500000, 40900000]
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vrfim v5, v4
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blr
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#_ REGISTER_OUT v4 [3FC00000, 40100000, 40500000, 40900000]
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#_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000]
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test_vrfim_2:
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#_ REGISTER_IN v4 [BFC00000, C0100000, C0500000, C0900000]
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vrfim v5, v4
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blr
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#_ REGISTER_OUT v4 [BFC00000, C0100000, C0500000, C0900000]
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#_ REGISTER_OUT v5 [C0000000, C0400000, C0800000, C0A00000]
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test_vrfim_3:
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#_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000]
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vrfim v5, v4
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blr
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#_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000]
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test_vrfim_4:
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#_ REGISTER_IN v4 [00000000, 80000000, 3F000000, BF000000]
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vrfim v5, v4
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blr
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#_ REGISTER_OUT v4 [00000000, 80000000, 3F000000, BF000000]
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#_ REGISTER_OUT v5 [00000000, 80000000, 00000000, BF800000]
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test_vrfim_5:
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#_ REGISTER_IN v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD]
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vrfim v5, v4
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blr
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#_ REGISTER_OUT v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD]
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#_ REGISTER_OUT v5 [00000000, 00000000, 3F800000, 3F800000]
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34
src/xenia/cpu/ppc/testing/instr_vrfip.s
Normal file
34
src/xenia/cpu/ppc/testing/instr_vrfip.s
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@@ -0,0 +1,34 @@
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test_vrfip_1:
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#_ REGISTER_IN v4 [3FC00000, 40100000, 40500000, 40900000]
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vrfip v5, v4
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blr
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#_ REGISTER_OUT v4 [3FC00000, 40100000, 40500000, 40900000]
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#_ REGISTER_OUT v5 [40000000, 40400000, 40800000, 40A00000]
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test_vrfip_2:
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#_ REGISTER_IN v4 [BFC00000, C0100000, C0500000, C0900000]
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vrfip v5, v4
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blr
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#_ REGISTER_OUT v4 [BFC00000, C0100000, C0500000, C0900000]
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#_ REGISTER_OUT v5 [BF800000, C0000000, C0400000, C0800000]
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test_vrfip_3:
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#_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000]
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vrfip v5, v4
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blr
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#_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000]
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test_vrfip_4:
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#_ REGISTER_IN v4 [00000000, 80000000, 3F000000, BF000000]
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vrfip v5, v4
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blr
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#_ REGISTER_OUT v4 [00000000, 80000000, 3F000000, BF000000]
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#_ REGISTER_OUT v5 [00000000, 80000000, 3F800000, 80000000]
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test_vrfip_5:
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#_ REGISTER_IN v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD]
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vrfip v5, v4
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blr
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#_ REGISTER_OUT v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD]
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#_ REGISTER_OUT v5 [3F800000, 3F800000, 3F800000, 40000000]
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34
src/xenia/cpu/ppc/testing/instr_vrfiz.s
Normal file
34
src/xenia/cpu/ppc/testing/instr_vrfiz.s
Normal file
@@ -0,0 +1,34 @@
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test_vrfiz_1:
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#_ REGISTER_IN v4 [3FC00000, 40100000, 40500000, 40900000]
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vrfiz v5, v4
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blr
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#_ REGISTER_OUT v4 [3FC00000, 40100000, 40500000, 40900000]
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#_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000]
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test_vrfiz_2:
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#_ REGISTER_IN v4 [BFC00000, C0100000, C0500000, C0900000]
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vrfiz v5, v4
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blr
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#_ REGISTER_OUT v4 [BFC00000, C0100000, C0500000, C0900000]
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#_ REGISTER_OUT v5 [BF800000, C0000000, C0400000, C0800000]
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test_vrfiz_3:
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#_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000]
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vrfiz v5, v4
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blr
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#_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000]
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test_vrfiz_4:
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#_ REGISTER_IN v4 [00000000, 80000000, 3F000000, BF000000]
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vrfiz v5, v4
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blr
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#_ REGISTER_OUT v4 [00000000, 80000000, 3F000000, BF000000]
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#_ REGISTER_OUT v5 [00000000, 80000000, 00000000, 80000000]
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test_vrfiz_5:
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#_ REGISTER_IN v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD]
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vrfiz v5, v4
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blr
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#_ REGISTER_OUT v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD]
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#_ REGISTER_OUT v5 [00000000, 00000000, 3F800000, 3F800000]
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34
src/xenia/cpu/ppc/testing/instr_vrsqrtefp.s
Normal file
34
src/xenia/cpu/ppc/testing/instr_vrsqrtefp.s
Normal file
@@ -0,0 +1,34 @@
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test_vrsqrtefp_1:
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#_ REGISTER_IN v4 [3F800000, 40000000, 40800000, 41000000]
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vrsqrtefp v5, v4
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blr
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#_ REGISTER_OUT v4 [3F800000, 40000000, 40800000, 41000000]
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#_ REGISTER_OUT v5 [3F7FF400, 3F34FD00, 3EFFF400, 3EB4FD00]
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test_vrsqrtefp_2:
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#_ REGISTER_IN v4 [40400000, 40A00000, 41200000, 41800000]
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vrsqrtefp v5, v4
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blr
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#_ REGISTER_OUT v4 [40400000, 40A00000, 41200000, 41800000]
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#_ REGISTER_OUT v5 [3F13CA00, 3EE4F200, 3EA1E400, 3E7FF400]
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test_vrsqrtefp_3:
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#_ REGISTER_IN v4 [41900000, 41A00000, 41B00000, 41C00000]
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vrsqrtefp v5, v4
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blr
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#_ REGISTER_OUT v4 [41900000, 41A00000, 41B00000, 41C00000]
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#_ REGISTER_OUT v5 [3E715400, 3E64F200, 3E5A4C00, 3E510200]
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test_vrsqrtefp_4:
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#_ REGISTER_IN v4 [3E800000, 3F000000, 3F400000, 3F600000]
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vrsqrtefp v5, v4
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blr
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#_ REGISTER_OUT v4 [3E800000, 3F000000, 3F400000, 3F600000]
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#_ REGISTER_OUT v5 [3FFFF400, 3FB4FD00, 3F93CA00, 3F88D400]
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test_vrsqrtefp_5:
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#_ REGISTER_IN v4 [42480000, 42C80000, 43480000, 43C80000]
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vrsqrtefp v5, v4
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blr
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#_ REGISTER_OUT v4 [42480000, 42C80000, 43480000, 43C80000]
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#_ REGISTER_OUT v5 [3E10CE00, 3DCCCA00, 3D90CE00, 3D4CCA00]
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