From b6af8ed5453b63bc0ae38242c3d41f87386121d3 Mon Sep 17 00:00:00 2001 From: "Herman S." <429230+has207@users.noreply.github.com> Date: Tue, 14 Oct 2025 20:24:59 +0900 Subject: [PATCH] [Testing] Add more tests for logic, conversion and fp instructions --- src/xenia/cpu/ppc/testing/instr_vcfux.s | 34 +++++++++++++ src/xenia/cpu/ppc/testing/instr_vnmsubfp.s | 54 +++++++++++++++++++++ src/xenia/cpu/ppc/testing/instr_vnor.s | 44 +++++++++++++++++ src/xenia/cpu/ppc/testing/instr_vrefp.s | 34 +++++++++++++ src/xenia/cpu/ppc/testing/instr_vrfim.s | 34 +++++++++++++ src/xenia/cpu/ppc/testing/instr_vrfip.s | 34 +++++++++++++ src/xenia/cpu/ppc/testing/instr_vrfiz.s | 34 +++++++++++++ src/xenia/cpu/ppc/testing/instr_vrsqrtefp.s | 34 +++++++++++++ 8 files changed, 302 insertions(+) create mode 100644 src/xenia/cpu/ppc/testing/instr_vcfux.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vnmsubfp.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vnor.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vrefp.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vrfim.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vrfip.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vrfiz.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vrsqrtefp.s diff --git a/src/xenia/cpu/ppc/testing/instr_vcfux.s b/src/xenia/cpu/ppc/testing/instr_vcfux.s new file mode 100644 index 000000000..08a9f2143 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vcfux.s @@ -0,0 +1,34 @@ +test_vcfux_1: + #_ REGISTER_IN v4 [00000001, 00000002, 00000003, 00000004] + vcfux v5, v4, 0 + blr + #_ REGISTER_OUT v4 [00000001, 00000002, 00000003, 00000004] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000] + +test_vcfux_2: + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + vcfux v5, v4, 0 + blr + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] + +test_vcfux_3: + #_ REGISTER_IN v4 [00000008, 00000010, 00000020, 00000040] + vcfux v5, v4, 1 + blr + #_ REGISTER_OUT v4 [00000008, 00000010, 00000020, 00000040] + #_ REGISTER_OUT v5 [40800000, 41000000, 41800000, 42000000] + +test_vcfux_4: + #_ REGISTER_IN v4 [00000100, 00000200, 00000400, 00000800] + vcfux v5, v4, 4 + blr + #_ REGISTER_OUT v4 [00000100, 00000200, 00000400, 00000800] + #_ REGISTER_OUT v5 [41800000, 42000000, 42800000, 43000000] + +test_vcfux_5: + #_ REGISTER_IN v4 [000000FF, 000001FF, 000003FF, 000007FF] + vcfux v5, v4, 0 + blr + #_ REGISTER_OUT v4 [000000FF, 000001FF, 000003FF, 000007FF] + #_ REGISTER_OUT v5 [437F0000, 43FF8000, 447FC000, 44FFE000] diff --git a/src/xenia/cpu/ppc/testing/instr_vnmsubfp.s b/src/xenia/cpu/ppc/testing/instr_vnmsubfp.s new file mode 100644 index 000000000..5f1b2b5a9 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vnmsubfp.s @@ -0,0 +1,54 @@ +test_vnmsubfp_1: + #_ REGISTER_IN v3 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v5 [40000000, 40000000, 40000000, 40000000] + vnmsubfp v6, v3, v5, v4 + blr + #_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v6 [C0400000, C0400000, C0400000, C0400000] + +test_vnmsubfp_2: + #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_IN v5 [40000000, 40400000, 40800000, 40A00000] + vnmsubfp v6, v3, v5, v4 + blr + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v5 [40000000, 40400000, 40800000, 40A00000] + #_ REGISTER_OUT v6 [3F800000, 40000000, 40400000, 40800000] + +test_vnmsubfp_3: + #_ REGISTER_IN v3 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_IN v5 [40000000, 40000000, 40000000, 40000000] + vnmsubfp v6, v3, v5, v4 + blr + #_ REGISTER_OUT v3 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v5 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v6 [C0000000, C0800000, C0C00000, C1000000] + +test_vnmsubfp_4: + #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v5 [3F800000, 3F800000, 3F800000, 3F800000] + vnmsubfp v6, v3, v5, v4 + blr + #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v6 [80000000, 80000000, 80000000, 80000000] + +test_vnmsubfp_5: + #_ REGISTER_IN v3 [40400000, 40400000, 40400000, 40400000] + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v5 [40000000, 40000000, 40000000, 40000000] + vnmsubfp v6, v3, v5, v4 + blr + #_ REGISTER_OUT v3 [40400000, 40400000, 40400000, 40400000] + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v6 [C0A00000, C0A00000, C0A00000, C0A00000] diff --git a/src/xenia/cpu/ppc/testing/instr_vnor.s b/src/xenia/cpu/ppc/testing/instr_vnor.s new file mode 100644 index 000000000..c278e4308 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vnor.s @@ -0,0 +1,44 @@ +test_vnor_1: + #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + vnor v5, v3, v4 + blr + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + +test_vnor_2: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + vnor v5, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] + +test_vnor_3: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + vnor v5, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] + +test_vnor_4: + #_ REGISTER_IN v3 [F0F0F0F0, F0F0F0F0, F0F0F0F0, F0F0F0F0] + #_ REGISTER_IN v4 [0F0F0F0F, 0F0F0F0F, 0F0F0F0F, 0F0F0F0F] + vnor v5, v3, v4 + blr + #_ REGISTER_OUT v3 [F0F0F0F0, F0F0F0F0, F0F0F0F0, F0F0F0F0] + #_ REGISTER_OUT v4 [0F0F0F0F, 0F0F0F0F, 0F0F0F0F, 0F0F0F0F] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] + +test_vnor_5: + #_ REGISTER_IN v3 [AAAAAAAA, 55555555, CCCCCCCC, 33333333] + #_ REGISTER_IN v4 [55555555, AAAAAAAA, 33333333, CCCCCCCC] + vnor v5, v3, v4 + blr + #_ REGISTER_OUT v3 [AAAAAAAA, 55555555, CCCCCCCC, 33333333] + #_ REGISTER_OUT v4 [55555555, AAAAAAAA, 33333333, CCCCCCCC] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] diff --git a/src/xenia/cpu/ppc/testing/instr_vrefp.s b/src/xenia/cpu/ppc/testing/instr_vrefp.s new file mode 100644 index 000000000..dd26131d7 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vrefp.s @@ -0,0 +1,34 @@ +test_vrefp_1: + #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000] + vrefp v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v5 [3F800000, 3F000000, 3EAAAAAB, 3E800000] + +test_vrefp_2: + #_ REGISTER_IN v4 [40A00000, 40C00000, 40E00000, 41000000] + vrefp v5, v4 + blr + #_ REGISTER_OUT v4 [40A00000, 40C00000, 40E00000, 41000000] + #_ REGISTER_OUT v5 [3E4CCCCD, 3E2AAAAB, 3E124925, 3E000000] + +test_vrefp_3: + #_ REGISTER_IN v4 [3F000000, 3E800000, 3E000000, 3D800000] + vrefp v5, v4 + blr + #_ REGISTER_OUT v4 [3F000000, 3E800000, 3E000000, 3D800000] + #_ REGISTER_OUT v5 [40000000, 40800000, 41000000, 41800000] + +test_vrefp_4: + #_ REGISTER_IN v4 [BF800000, C0000000, C0400000, C0800000] + vrefp v5, v4 + blr + #_ REGISTER_OUT v4 [BF800000, C0000000, C0400000, C0800000] + #_ REGISTER_OUT v5 [BF800000, BF000000, BEAAAAAB, BE800000] + +test_vrefp_5: + #_ REGISTER_IN v4 [42C80000, 43480000, 43960000, 44160000] + vrefp v5, v4 + blr + #_ REGISTER_OUT v4 [42C80000, 43480000, 43960000, 44160000] + #_ REGISTER_OUT v5 [3C23D70A, 3BA3D70A, 3B5A740E, 3ADA740E] diff --git a/src/xenia/cpu/ppc/testing/instr_vrfim.s b/src/xenia/cpu/ppc/testing/instr_vrfim.s new file mode 100644 index 000000000..f21ec4d86 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vrfim.s @@ -0,0 +1,34 @@ +test_vrfim_1: + #_ REGISTER_IN v4 [3FC00000, 40100000, 40500000, 40900000] + vrfim v5, v4 + blr + #_ REGISTER_OUT v4 [3FC00000, 40100000, 40500000, 40900000] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000] + +test_vrfim_2: + #_ REGISTER_IN v4 [BFC00000, C0100000, C0500000, C0900000] + vrfim v5, v4 + blr + #_ REGISTER_OUT v4 [BFC00000, C0100000, C0500000, C0900000] + #_ REGISTER_OUT v5 [C0000000, C0400000, C0800000, C0A00000] + +test_vrfim_3: + #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000] + vrfim v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000] + +test_vrfim_4: + #_ REGISTER_IN v4 [00000000, 80000000, 3F000000, BF000000] + vrfim v5, v4 + blr + #_ REGISTER_OUT v4 [00000000, 80000000, 3F000000, BF000000] + #_ REGISTER_OUT v5 [00000000, 80000000, 00000000, BF800000] + +test_vrfim_5: + #_ REGISTER_IN v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD] + vrfim v5, v4 + blr + #_ REGISTER_OUT v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD] + #_ REGISTER_OUT v5 [00000000, 00000000, 3F800000, 3F800000] diff --git a/src/xenia/cpu/ppc/testing/instr_vrfip.s b/src/xenia/cpu/ppc/testing/instr_vrfip.s new file mode 100644 index 000000000..5c37e70f3 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vrfip.s @@ -0,0 +1,34 @@ +test_vrfip_1: + #_ REGISTER_IN v4 [3FC00000, 40100000, 40500000, 40900000] + vrfip v5, v4 + blr + #_ REGISTER_OUT v4 [3FC00000, 40100000, 40500000, 40900000] + #_ REGISTER_OUT v5 [40000000, 40400000, 40800000, 40A00000] + +test_vrfip_2: + #_ REGISTER_IN v4 [BFC00000, C0100000, C0500000, C0900000] + vrfip v5, v4 + blr + #_ REGISTER_OUT v4 [BFC00000, C0100000, C0500000, C0900000] + #_ REGISTER_OUT v5 [BF800000, C0000000, C0400000, C0800000] + +test_vrfip_3: + #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000] + vrfip v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000] + +test_vrfip_4: + #_ REGISTER_IN v4 [00000000, 80000000, 3F000000, BF000000] + vrfip v5, v4 + blr + #_ REGISTER_OUT v4 [00000000, 80000000, 3F000000, BF000000] + #_ REGISTER_OUT v5 [00000000, 80000000, 3F800000, 80000000] + +test_vrfip_5: + #_ REGISTER_IN v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD] + vrfip v5, v4 + blr + #_ REGISTER_OUT v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD] + #_ REGISTER_OUT v5 [3F800000, 3F800000, 3F800000, 40000000] diff --git a/src/xenia/cpu/ppc/testing/instr_vrfiz.s b/src/xenia/cpu/ppc/testing/instr_vrfiz.s new file mode 100644 index 000000000..b8a60d43d --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vrfiz.s @@ -0,0 +1,34 @@ +test_vrfiz_1: + #_ REGISTER_IN v4 [3FC00000, 40100000, 40500000, 40900000] + vrfiz v5, v4 + blr + #_ REGISTER_OUT v4 [3FC00000, 40100000, 40500000, 40900000] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000] + +test_vrfiz_2: + #_ REGISTER_IN v4 [BFC00000, C0100000, C0500000, C0900000] + vrfiz v5, v4 + blr + #_ REGISTER_OUT v4 [BFC00000, C0100000, C0500000, C0900000] + #_ REGISTER_OUT v5 [BF800000, C0000000, C0400000, C0800000] + +test_vrfiz_3: + #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000] + vrfiz v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000] + +test_vrfiz_4: + #_ REGISTER_IN v4 [00000000, 80000000, 3F000000, BF000000] + vrfiz v5, v4 + blr + #_ REGISTER_OUT v4 [00000000, 80000000, 3F000000, BF000000] + #_ REGISTER_OUT v5 [00000000, 80000000, 00000000, 80000000] + +test_vrfiz_5: + #_ REGISTER_IN v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD] + vrfiz v5, v4 + blr + #_ REGISTER_OUT v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD] + #_ REGISTER_OUT v5 [00000000, 00000000, 3F800000, 3F800000] diff --git a/src/xenia/cpu/ppc/testing/instr_vrsqrtefp.s b/src/xenia/cpu/ppc/testing/instr_vrsqrtefp.s new file mode 100644 index 000000000..390dfb197 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vrsqrtefp.s @@ -0,0 +1,34 @@ +test_vrsqrtefp_1: + #_ REGISTER_IN v4 [3F800000, 40000000, 40800000, 41000000] + vrsqrtefp v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 40000000, 40800000, 41000000] + #_ REGISTER_OUT v5 [3F7FF400, 3F34FD00, 3EFFF400, 3EB4FD00] + +test_vrsqrtefp_2: + #_ REGISTER_IN v4 [40400000, 40A00000, 41200000, 41800000] + vrsqrtefp v5, v4 + blr + #_ REGISTER_OUT v4 [40400000, 40A00000, 41200000, 41800000] + #_ REGISTER_OUT v5 [3F13CA00, 3EE4F200, 3EA1E400, 3E7FF400] + +test_vrsqrtefp_3: + #_ REGISTER_IN v4 [41900000, 41A00000, 41B00000, 41C00000] + vrsqrtefp v5, v4 + blr + #_ REGISTER_OUT v4 [41900000, 41A00000, 41B00000, 41C00000] + #_ REGISTER_OUT v5 [3E715400, 3E64F200, 3E5A4C00, 3E510200] + +test_vrsqrtefp_4: + #_ REGISTER_IN v4 [3E800000, 3F000000, 3F400000, 3F600000] + vrsqrtefp v5, v4 + blr + #_ REGISTER_OUT v4 [3E800000, 3F000000, 3F400000, 3F600000] + #_ REGISTER_OUT v5 [3FFFF400, 3FB4FD00, 3F93CA00, 3F88D400] + +test_vrsqrtefp_5: + #_ REGISTER_IN v4 [42480000, 42C80000, 43480000, 43C80000] + vrsqrtefp v5, v4 + blr + #_ REGISTER_OUT v4 [42480000, 42C80000, 43480000, 43C80000] + #_ REGISTER_OUT v5 [3E10CE00, 3DCCCA00, 3D90CE00, 3D4CCA00]