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SPIR-V: Batch predicated instructions together into a single block.

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Add Post-Translation validation.
Fix a couple of type-related typos.
This commit is contained in:
Dr. Chat
2016-04-09 21:03:44 -05:00
parent a1c9540063
commit b7f2c93d73
4 changed files with 210 additions and 112 deletions
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19
src/xenia/gpu/shader_translator.cc
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@@ -986,16 +986,19 @@ void ShaderTranslator::TranslateAluInstruction(const AluInstruction& op) {
return;
}
ParsedAluInstruction instr;
if (op.has_vector_op()) {
const auto& opcode_info =
alu_vector_opcode_infos_[static_cast<int>(op.vector_opcode())];
ParseAluVectorInstruction(op, opcode_info);
ParseAluVectorInstruction(op, opcode_info, instr);
ProcessAluInstruction(instr);
}
if (op.has_scalar_op()) {
const auto& opcode_info =
alu_scalar_opcode_infos_[static_cast<int>(op.scalar_opcode())];
ParseAluScalarInstruction(op, opcode_info);
ParseAluScalarInstruction(op, opcode_info, instr);
ProcessAluInstruction(instr);
}
}
@@ -1088,8 +1091,8 @@ void ParseAluInstructionOperandSpecial(const AluInstruction& op,
}
void ShaderTranslator::ParseAluVectorInstruction(
const AluInstruction& op, const AluOpcodeInfo& opcode_info) {
ParsedAluInstruction i;
const AluInstruction& op, const AluOpcodeInfo& opcode_info,
ParsedAluInstruction& i) {
i.dword_index = 0;
i.type = ParsedAluInstruction::Type::kVector;
i.vector_opcode = op.vector_opcode();
@@ -1203,13 +1206,11 @@ void ShaderTranslator::ParseAluVectorInstruction(
}
i.Disassemble(&ucode_disasm_buffer_);
ProcessAluInstruction(i);
}
void ShaderTranslator::ParseAluScalarInstruction(
const AluInstruction& op, const AluOpcodeInfo& opcode_info) {
ParsedAluInstruction i;
const AluInstruction& op, const AluOpcodeInfo& opcode_info,
ParsedAluInstruction& i) {
i.dword_index = 0;
i.type = ParsedAluInstruction::Type::kScalar;
i.scalar_opcode = op.scalar_opcode();
@@ -1319,8 +1320,6 @@ void ShaderTranslator::ParseAluScalarInstruction(
}
i.Disassemble(&ucode_disasm_buffer_);
ProcessAluInstruction(i);
}
} // namespace gpu