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Merge branch 'master' into vulkan

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This commit is contained in:
Triang3l
2022-02-13 23:25:39 +03:00
parent 8ccb00d03d e57db52285
commit b8c9d5bb8c
40 changed files with 368 additions and 16034 deletions
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70
src/xenia/gpu/d3d12/d3d12_command_processor.cc
View File

@@ -103,22 +103,6 @@ void D3D12CommandProcessor::RestoreEdramSnapshot(const void* snapshot) {
render_target_cache_->RestoreEdramSnapshot(snapshot);
}
uint32_t D3D12CommandProcessor::GetCurrentColorMask(
uint32_t shader_writes_color_targets) const {
auto& regs = *register_file_;
if (regs.Get<reg::RB_MODECONTROL>().edram_mode !=
xenos::ModeControl::kColorDepth) {
return 0;
}
uint32_t color_mask = regs[XE_GPU_REG_RB_COLOR_MASK].u32 & 0xFFFF;
for (uint32_t i = 0; i < 4; ++i) {
if (!(shader_writes_color_targets & (1 << i))) {
color_mask &= ~(0xF << (i * 4));
}
}
return color_mask;
}
void D3D12CommandProcessor::PushTransitionBarrier(
ID3D12Resource* resource, D3D12_RESOURCE_STATES old_state,
D3D12_RESOURCE_STATES new_state, UINT subresource) {
@@ -699,7 +683,7 @@ void D3D12CommandProcessor::ReleaseScratchGPUBuffer(
void D3D12CommandProcessor::SetExternalPipeline(ID3D12PipelineState* pipeline) {
if (current_external_pipeline_ != pipeline) {
current_external_pipeline_ = pipeline;
current_cached_pipeline_ = nullptr;
current_guest_pipeline_ = nullptr;
deferred_command_list_.D3DSetPipelineState(pipeline);
}
}
@@ -723,7 +707,7 @@ void D3D12CommandProcessor::SetViewport(const D3D12_VIEWPORT& viewport) {
ff_viewport_update_needed_ |= ff_viewport_.MaxDepth != viewport.MaxDepth;
if (ff_viewport_update_needed_) {
ff_viewport_ = viewport;
deferred_command_list_.RSSetViewport(viewport);
deferred_command_list_.RSSetViewport(ff_viewport_);
ff_viewport_update_needed_ = false;
}
}
@@ -735,7 +719,7 @@ void D3D12CommandProcessor::SetScissorRect(const D3D12_RECT& scissor_rect) {
ff_scissor_update_needed_ |= ff_scissor_.bottom != scissor_rect.bottom;
if (ff_scissor_update_needed_) {
ff_scissor_ = scissor_rect;
deferred_command_list_.RSSetScissorRect(scissor_rect);
deferred_command_list_.RSSetScissorRect(ff_scissor_);
ff_scissor_update_needed_ = false;
}
}
@@ -2152,10 +2136,12 @@ bool D3D12CommandProcessor::IssueDraw(xenos::PrimitiveType primitive_type,
: DxbcShaderTranslator::Modification(0);
// Set up the render targets - this may perform dispatches and draws.
uint32_t pixel_shader_writes_color_targets =
pixel_shader ? pixel_shader->writes_color_targets() : 0;
uint32_t normalized_color_mask =
pixel_shader ? draw_util::GetNormalizedColorMask(
regs, pixel_shader->writes_color_targets())
: 0;
if (!render_target_cache_->Update(is_rasterization_done,
pixel_shader_writes_color_targets)) {
normalized_color_mask)) {
return false;
}
@@ -2186,7 +2172,8 @@ bool D3D12CommandProcessor::IssueDraw(xenos::PrimitiveType primitive_type,
ID3D12RootSignature* root_signature;
if (!pipeline_cache_->ConfigurePipeline(
vertex_shader_translation, pixel_shader_translation,
primitive_processing_result, bound_depth_and_color_render_target_bits,
primitive_processing_result, normalized_color_mask,
bound_depth_and_color_render_target_bits,
bound_depth_and_color_render_target_formats, &pipeline_handle,
&root_signature)) {
return false;
@@ -2202,10 +2189,10 @@ bool D3D12CommandProcessor::IssueDraw(xenos::PrimitiveType primitive_type,
// Bind the pipeline after configuring it and doing everything that may bind
// other pipelines.
if (current_cached_pipeline_ != pipeline_handle) {
if (current_guest_pipeline_ != pipeline_handle) {
deferred_command_list_.SetPipelineStateHandle(
reinterpret_cast<void*>(pipeline_handle));
current_cached_pipeline_ = pipeline_handle;
current_guest_pipeline_ = pipeline_handle;
current_external_pipeline_ = nullptr;
}
@@ -2241,9 +2228,7 @@ bool D3D12CommandProcessor::IssueDraw(xenos::PrimitiveType primitive_type,
memexport_used, primitive_polygonal,
primitive_processing_result.line_loop_closing_index,
primitive_processing_result.host_index_endian, viewport_info,
used_texture_mask,
pixel_shader ? GetCurrentColorMask(pixel_shader->writes_color_targets())
: 0);
used_texture_mask, normalized_color_mask);
// Update constant buffers, descriptors and root parameters.
if (!UpdateBindings(vertex_shader, pixel_shader, root_signature)) {
@@ -2814,7 +2799,7 @@ bool D3D12CommandProcessor::BeginSubmission(bool is_guest_command) {
ff_scissor_update_needed_ = true;
ff_blend_factor_update_needed_ = true;
ff_stencil_ref_update_needed_ = true;
current_cached_pipeline_ = nullptr;
current_guest_pipeline_ = nullptr;
current_external_pipeline_ = nullptr;
current_graphics_root_signature_ = nullptr;
current_graphics_root_up_to_date_ = 0;
@@ -3071,19 +3056,18 @@ void D3D12CommandProcessor::UpdateFixedFunctionState(
const RegisterFile& regs = *register_file_;
// Blend factor.
float blend_factor[] = {
regs[XE_GPU_REG_RB_BLEND_RED].f32,
regs[XE_GPU_REG_RB_BLEND_GREEN].f32,
regs[XE_GPU_REG_RB_BLEND_BLUE].f32,
regs[XE_GPU_REG_RB_BLEND_ALPHA].f32,
};
// std::memcmp instead of != so in case of NaN, every draw won't be
// invalidating it.
ff_blend_factor_update_needed_ |=
ff_blend_factor_[0] != regs[XE_GPU_REG_RB_BLEND_RED].f32;
ff_blend_factor_update_needed_ |=
ff_blend_factor_[1] != regs[XE_GPU_REG_RB_BLEND_GREEN].f32;
ff_blend_factor_update_needed_ |=
ff_blend_factor_[2] != regs[XE_GPU_REG_RB_BLEND_BLUE].f32;
ff_blend_factor_update_needed_ |=
ff_blend_factor_[3] != regs[XE_GPU_REG_RB_BLEND_ALPHA].f32;
std::memcmp(ff_blend_factor_, blend_factor, sizeof(float) * 4) != 0;
if (ff_blend_factor_update_needed_) {
ff_blend_factor_[0] = regs[XE_GPU_REG_RB_BLEND_RED].f32;
ff_blend_factor_[1] = regs[XE_GPU_REG_RB_BLEND_GREEN].f32;
ff_blend_factor_[2] = regs[XE_GPU_REG_RB_BLEND_BLUE].f32;
ff_blend_factor_[3] = regs[XE_GPU_REG_RB_BLEND_ALPHA].f32;
std::memcpy(ff_blend_factor_, blend_factor, sizeof(float) * 4);
deferred_command_list_.D3DOMSetBlendFactor(ff_blend_factor_);
ff_blend_factor_update_needed_ = false;
}
@@ -3104,7 +3088,7 @@ void D3D12CommandProcessor::UpdateFixedFunctionState(
ff_stencil_ref_update_needed_ |= ff_stencil_ref_ != stencil_ref;
if (ff_stencil_ref_update_needed_) {
ff_stencil_ref_ = stencil_ref;
deferred_command_list_.D3DOMSetStencilRef(stencil_ref);
deferred_command_list_.D3DOMSetStencilRef(ff_stencil_ref_);
ff_stencil_ref_update_needed_ = false;
}
}
@@ -3114,7 +3098,7 @@ void D3D12CommandProcessor::UpdateSystemConstantValues(
bool shared_memory_is_uav, bool primitive_polygonal,
uint32_t line_loop_closing_index, xenos::Endian index_endian,
const draw_util::ViewportInfo& viewport_info, uint32_t used_texture_mask,
uint32_t color_mask) {
uint32_t normalized_color_mask) {
#if XE_UI_D3D12_FINE_GRAINED_DRAW_SCOPES
SCOPE_profile_cpu_f("gpu");
#endif // XE_UI_D3D12_FINE_GRAINED_DRAW_SCOPES
@@ -3161,7 +3145,7 @@ void D3D12CommandProcessor::UpdateSystemConstantValues(
// Get the mask for keeping previous color's components unmodified,
// or two UINT32_MAX if no colors actually existing in the RT are written.
DxbcShaderTranslator::ROV_GetColorFormatSystemConstants(
color_info.color_format, (color_mask >> (i * 4)) & 0b1111,
color_info.color_format, (normalized_color_mask >> (i * 4)) & 0b1111,
rt_clamp[i][0], rt_clamp[i][1], rt_clamp[i][2], rt_clamp[i][3],
rt_keep_masks[i][0], rt_keep_masks[i][1]);
}

16
src/xenia/gpu/d3d12/d3d12_command_processor.h
View File

@@ -83,16 +83,6 @@ class D3D12CommandProcessor : public CommandProcessor {
uint64_t GetCurrentFrame() const { return frame_current_; }
uint64_t GetCompletedFrame() const { return frame_completed_; }
// Gets the current color write mask, taking the pixel shader's write mask
// into account. If a shader doesn't write to a render target, it shouldn't be
// written to and it shouldn't be even bound - otherwise, in 4D5307E6, one
// render target is being destroyed by a shader not writing anything, and in
// 58410955, the result of clearing the top tile is being ignored because
// there are 4 render targets bound with the same EDRAM base (clearly not
// correct usage), but the shader only clears 1, and then EDRAM buffer stores
// conflict with each other.
uint32_t GetCurrentColorMask(uint32_t shader_writes_color_targets) const;
void PushTransitionBarrier(
ID3D12Resource* resource, D3D12_RESOURCE_STATES old_state,
D3D12_RESOURCE_STATES new_state,
@@ -362,7 +352,7 @@ class D3D12CommandProcessor : public CommandProcessor {
xenos::Endian index_endian,
const draw_util::ViewportInfo& viewport_info,
uint32_t used_texture_mask,
uint32_t color_mask);
uint32_t normalized_color_mask);
bool UpdateBindings(const D3D12Shader* vertex_shader,
const D3D12Shader* pixel_shader,
ID3D12RootSignature* root_signature);
@@ -593,8 +583,8 @@ class D3D12CommandProcessor : public CommandProcessor {
// Currently bound pipeline, either a graphics pipeline from the pipeline
// cache (with potentially deferred creation - current_external_pipeline_ is
// nullptr in this case) or a non-Xenos graphics or compute pipeline
// (current_cached_pipeline_ is nullptr in this case).
void* current_cached_pipeline_;
// (current_guest_pipeline_ is nullptr in this case).
void* current_guest_pipeline_;
ID3D12PipelineState* current_external_pipeline_;
// Currently bound graphics root signature.

45
src/xenia/gpu/d3d12/pipeline_cache.cc
View File

@@ -2,7 +2,7 @@
******************************************************************************
* Xenia : Xbox 360 Emulator Research Project *
******************************************************************************
* Copyright 2020 Ben Vanik. All rights reserved. *
* Copyright 2022 Ben Vanik. All rights reserved. *
* Released under the BSD license - see LICENSE in the root for more details. *
******************************************************************************
*/
@@ -934,6 +934,7 @@ bool PipelineCache::ConfigurePipeline(
D3D12Shader::D3D12Translation* vertex_shader,
D3D12Shader::D3D12Translation* pixel_shader,
const PrimitiveProcessor::ProcessingResult& primitive_processing_result,
uint32_t normalized_color_mask,
uint32_t bound_depth_and_color_render_target_bits,
const uint32_t* bound_depth_and_color_render_target_formats,
void** pipeline_handle_out, ID3D12RootSignature** root_signature_out) {
@@ -1005,7 +1006,7 @@ bool PipelineCache::ConfigurePipeline(
PipelineRuntimeDescription runtime_description;
if (!GetCurrentStateDescription(
vertex_shader, pixel_shader, primitive_processing_result,
bound_depth_and_color_render_target_bits,
normalized_color_mask, bound_depth_and_color_render_target_bits,
bound_depth_and_color_render_target_formats, runtime_description)) {
return false;
}
@@ -1272,6 +1273,7 @@ bool PipelineCache::GetCurrentStateDescription(
D3D12Shader::D3D12Translation* vertex_shader,
D3D12Shader::D3D12Translation* pixel_shader,
const PrimitiveProcessor::ProcessingResult& primitive_processing_result,
uint32_t normalized_color_mask,
uint32_t bound_depth_and_color_render_target_bits,
const uint32_t* bound_depth_and_color_render_target_formats,
PipelineRuntimeDescription& runtime_description_out) {
@@ -1409,7 +1411,6 @@ bool PipelineCache::GetCurrentStateDescription(
// rasterization will be disabled externally, or the draw call will be dropped
// early if the vertex shader doesn't export to memory.
bool cull_front, cull_back;
float poly_offset = 0.0f, poly_offset_scale = 0.0f;
if (primitive_polygonal) {
description_out.front_counter_clockwise = pa_su_sc_mode_cntl.face == 0;
cull_front = pa_su_sc_mode_cntl.cull_front != 0;
@@ -1433,10 +1434,6 @@ bool PipelineCache::GetCurrentStateDescription(
xenos::PolygonType::kTriangles) {
description_out.fill_mode_wireframe = 1;
}
if (!edram_rov_used && pa_su_sc_mode_cntl.poly_offset_front_enable) {
poly_offset = regs[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_OFFSET].f32;
poly_offset_scale = regs[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_SCALE].f32;
}
}
if (!cull_back) {
// Back faces aren't culled.
@@ -1444,13 +1441,6 @@ bool PipelineCache::GetCurrentStateDescription(
xenos::PolygonType::kTriangles) {
description_out.fill_mode_wireframe = 1;
}
// Prefer front depth bias because in general, front faces are the ones
// that are rendered (except for shadow volumes).
if (!edram_rov_used && pa_su_sc_mode_cntl.poly_offset_back_enable &&
poly_offset == 0.0f && poly_offset_scale == 0.0f) {
poly_offset = regs[XE_GPU_REG_PA_SU_POLY_OFFSET_BACK_OFFSET].f32;
poly_offset_scale = regs[XE_GPU_REG_PA_SU_POLY_OFFSET_BACK_SCALE].f32;
}
}
if (pa_su_sc_mode_cntl.poly_mode != xenos::PolygonModeEnable::kDualMode) {
description_out.fill_mode_wireframe = 0;
@@ -1459,24 +1449,23 @@ bool PipelineCache::GetCurrentStateDescription(
// Filled front faces only, without culling.
cull_front = false;
cull_back = false;
if (!edram_rov_used && pa_su_sc_mode_cntl.poly_offset_para_enable) {
poly_offset = regs[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_OFFSET].f32;
poly_offset_scale = regs[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_SCALE].f32;
}
}
if (!edram_rov_used) {
float poly_offset_host_scale = draw_util::GetD3D10PolygonOffsetFactor(
float polygon_offset, polygon_offset_scale;
draw_util::GetPreferredFacePolygonOffset(
regs, primitive_polygonal, polygon_offset_scale, polygon_offset);
float polygon_offset_host_scale = draw_util::GetD3D10PolygonOffsetFactor(
regs.Get<reg::RB_DEPTH_INFO>().depth_format, true);
// Using ceil here just in case a game wants the offset but passes a value
// that is too small - it's better to apply more offset than to make depth
// fighting worse or to disable the offset completely (Direct3D 12 takes an
// integer value).
description_out.depth_bias =
int32_t(std::ceil(std::abs(poly_offset * poly_offset_host_scale))) *
(poly_offset < 0.0f ? -1 : 1);
// "slope computed in subpixels ([...] 1/16)" - R5xx Acceleration.
int32_t(
std::ceil(std::abs(polygon_offset * polygon_offset_host_scale))) *
(polygon_offset < 0.0f ? -1 : 1);
description_out.depth_bias_slope_scaled =
poly_offset_scale * xenos::kPolygonOffsetScaleSubpixelUnit;
polygon_offset_scale * xenos::kPolygonOffsetScaleSubpixelUnit;
}
if (tessellated && cvars::d3d12_tessellation_wireframe) {
description_out.fill_mode_wireframe = 1;
@@ -1547,10 +1536,6 @@ bool PipelineCache::GetCurrentStateDescription(
// Render targets and blending state. 32 because of 0x1F mask, for safety
// (all unknown to zero).
uint32_t color_mask =
pixel_shader ? command_processor_.GetCurrentColorMask(
pixel_shader->shader().writes_color_targets())
: 0;
static const PipelineBlendFactor kBlendFactorMap[32] = {
/* 0 */ PipelineBlendFactor::kZero,
/* 1 */ PipelineBlendFactor::kOne,
@@ -1622,8 +1607,7 @@ bool PipelineCache::GetCurrentStateDescription(
reg::RB_COLOR_INFO::rt_register_indices[i]);
rt.format = xenos::ColorRenderTargetFormat(
bound_depth_and_color_render_target_formats[1 + i]);
// TODO(Triang3l): Normalize unused bits of the color write mask.
rt.write_mask = (color_mask >> (i * 4)) & 0xF;
rt.write_mask = (normalized_color_mask >> (i * 4)) & 0xF;
if (rt.write_mask) {
auto blendcontrol = regs.Get<reg::RB_BLENDCONTROL>(
reg::RB_BLENDCONTROL::rt_register_indices[i]);
@@ -2017,9 +2001,6 @@ ID3D12PipelineState* PipelineCache::CreateD3D12Pipeline(
}
D3D12_RENDER_TARGET_BLEND_DESC& blend_desc =
state_desc.BlendState.RenderTarget[i];
// Treat 1 * src + 0 * dest as disabled blending (there are opaque
// surfaces drawn with blending enabled, but it's 1 * src + 0 * dest, in
// 415607E6 - GPU performance is better when not blending.
if (rt.src_blend != PipelineBlendFactor::kOne ||
rt.dest_blend != PipelineBlendFactor::kZero ||
rt.blend_op != xenos::BlendOp::kAdd ||

2
src/xenia/gpu/d3d12/pipeline_cache.h
View File

@@ -82,6 +82,7 @@ class PipelineCache {
D3D12Shader::D3D12Translation* vertex_shader,
D3D12Shader::D3D12Translation* pixel_shader,
const PrimitiveProcessor::ProcessingResult& primitive_processing_result,
uint32_t normalized_color_mask,
uint32_t bound_depth_and_color_render_target_bits,
const uint32_t* bound_depth_and_color_render_targets_formats,
void** pipeline_handle_out, ID3D12RootSignature** root_signature_out);
@@ -247,6 +248,7 @@ class PipelineCache {
D3D12Shader::D3D12Translation* vertex_shader,
D3D12Shader::D3D12Translation* pixel_shader,
const PrimitiveProcessor::ProcessingResult& primitive_processing_result,
uint32_t normalized_color_mask,
uint32_t bound_depth_and_color_render_target_bits,
const uint32_t* bound_depth_and_color_render_target_formats,
PipelineRuntimeDescription& runtime_description_out);

75
src/xenia/gpu/draw_util.cc
View File

@@ -2,7 +2,7 @@
******************************************************************************
* Xenia : Xbox 360 Emulator Research Project *
******************************************************************************
* Copyright 2020 Ben Vanik. All rights reserved. *
* Copyright 2022 Ben Vanik. All rights reserved. *
* Released under the BSD license - see LICENSE in the root for more details. *
******************************************************************************
*/
@@ -68,6 +68,36 @@ const int8_t kD3D10StandardSamplePositions2x[2][2] = {{4, 4}, {-4, -4}};
const int8_t kD3D10StandardSamplePositions4x[4][2] = {
{-2, -6}, {6, -2}, {-6, 2}, {2, 6}};
void GetPreferredFacePolygonOffset(const RegisterFile& regs,
bool primitive_polygonal, float& scale_out,
float& offset_out) {
float scale = 0.0f, offset = 0.0f;
auto pa_su_sc_mode_cntl = regs.Get<reg::PA_SU_SC_MODE_CNTL>();
if (primitive_polygonal) {
// Prefer the front polygon offset because in general, front faces are the
// ones that are rendered (except for shadow volumes).
if (pa_su_sc_mode_cntl.poly_offset_front_enable &&
!pa_su_sc_mode_cntl.cull_front) {
scale = regs[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_SCALE].f32;
offset = regs[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_OFFSET].f32;
}
if (pa_su_sc_mode_cntl.poly_offset_back_enable &&
!pa_su_sc_mode_cntl.cull_back && !scale && !offset) {
scale = regs[XE_GPU_REG_PA_SU_POLY_OFFSET_BACK_SCALE].f32;
offset = regs[XE_GPU_REG_PA_SU_POLY_OFFSET_BACK_OFFSET].f32;
}
} else {
// Non-triangle primitives use the front offset, but it's toggled via
// poly_offset_para_enable.
if (pa_su_sc_mode_cntl.poly_offset_para_enable) {
scale = regs[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_SCALE].f32;
offset = regs[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_OFFSET].f32;
}
}
scale_out = scale;
offset_out = offset;
}
bool IsPixelShaderNeededWithRasterization(const Shader& shader,
const RegisterFile& regs) {
assert_true(shader.type() == xenos::ShaderType::kPixel);
@@ -550,6 +580,49 @@ void GetScissor(const RegisterFile& regs, Scissor& scissor_out,
scissor_out.extent[1] = uint32_t(br_y - tl_y);
}
uint32_t GetNormalizedColorMask(const RegisterFile& regs,
uint32_t pixel_shader_writes_color_targets) {
if (regs.Get<reg::RB_MODECONTROL>().edram_mode !=
xenos::ModeControl::kColorDepth) {
return 0;
}
uint32_t normalized_color_mask = 0;
uint32_t rb_color_mask = regs[XE_GPU_REG_RB_COLOR_MASK].u32;
for (uint32_t i = 0; i < xenos::kMaxColorRenderTargets; ++i) {
// Exclude the render targets not statically written to by the pixel shader.
// If the shader doesn't write to a render target, it shouldn't be written
// to, and no ownership transfers should happen to it on the host even -
// otherwise, in 4D5307E6, one render target is being destroyed by a shader
// not writing anything, and in 58410955, the result of clearing the top
// tile is being ignored because there are 4 render targets bound with the
// same EDRAM base (clearly not correct usage), but the shader only clears
// 1, and then ownership of EDRAM portions by host render targets is
// conflicting.
if (!(pixel_shader_writes_color_targets & (uint32_t(1) << i))) {
continue;
}
// Check if any existing component is written to.
uint32_t format_component_mask =
(uint32_t(1) << xenos::GetColorRenderTargetFormatComponentCount(
regs.Get<reg::RB_COLOR_INFO>(
reg::RB_COLOR_INFO::rt_register_indices[i])
.color_format)) -
1;
uint32_t rt_write_mask = (rb_color_mask >> (4 * i)) & format_component_mask;
if (!rt_write_mask) {
continue;
}
// Mark the non-existent components as written so in the host driver, no
// slow path (involving reading and merging components) is taken if the
// driver doesn't perform this check internally, and some components are not
// included in the mask even though they actually don't exist in the format.
rt_write_mask |= 0b1111 & ~format_component_mask;
// Add to the normalized mask.
normalized_color_mask |= rt_write_mask << (4 * i);
}
return normalized_color_mask;
}
xenos::CopySampleSelect SanitizeCopySampleSelect(
xenos::CopySampleSelect copy_sample_select, xenos::MsaaSamples msaa_samples,
bool is_depth) {

23
src/xenia/gpu/draw_util.h
View File

@@ -2,7 +2,7 @@
******************************************************************************
* Xenia : Xbox 360 Emulator Research Project *
******************************************************************************
* Copyright 2020 Ben Vanik. All rights reserved. *
* Copyright 2022 Ben Vanik. All rights reserved. *
* Released under the BSD license - see LICENSE in the root for more details. *
******************************************************************************
*/
@@ -122,6 +122,16 @@ constexpr float GetD3D10PolygonOffsetFactor(
return float24_as_0_to_0_5 ? kFloat24Scale * 0.5f : kFloat24Scale;
}
// For hosts not supporting separate front and back polygon offsets, returns the
// polygon offset for the face which likely needs the offset the most (and that
// will not be culled). The values returned will have the units of the original
// registers (the scale is for 1/16 subpixels, multiply by
// xenos::kPolygonOffsetScaleSubpixelUnit outside if the value for pixels is
// needed).
void GetPreferredFacePolygonOffset(const RegisterFile& regs,
bool primitive_polygonal, float& scale_out,
float& offset_out);
inline bool DoesCoverageDependOnAlpha(reg::RB_COLORCONTROL rb_colorcontrol) {
return (rb_colorcontrol.alpha_test_enable &&
rb_colorcontrol.alpha_func != xenos::CompareFunction::kAlways) ||
@@ -186,6 +196,17 @@ struct Scissor {
void GetScissor(const RegisterFile& regs, Scissor& scissor_out,
bool clamp_to_surface_pitch = true);
// Returns the color component write mask for the draw command taking into
// account which color targets are written to by the pixel shader, as well as
// components that don't exist in the formats of the render targets (render
// targets with only non-existent components written are skipped, but
// non-existent components are forced to written if some existing components of
// the render target are actually used to make sure the host driver doesn't try
// to take a slow path involving reading and mixing if there are any disabled
// components even if they don't actually exist).
uint32_t GetNormalizedColorMask(const RegisterFile& regs,
uint32_t pixel_shader_writes_color_targets);
// Scales, and shift amounts of the upper 32 bits of the 32x32=64-bit
// multiplication result, for fast division and multiplication by
// EDRAM-tile-related amounts.

3
src/xenia/gpu/null/premake5.lua
View File

@@ -13,6 +13,7 @@ project("xenia-gpu-null")
"xenia-ui-vulkan",
"xxhash",
})
defines({
includedirs({
project_root.."/third_party/Vulkan-Headers/include",
})
local_platform_files()

6
src/xenia/gpu/premake5.lua
View File

@@ -15,7 +15,8 @@ project("xenia-gpu")
"xenia-ui",
"xxhash",
})
defines({
includedirs({
project_root.."/third_party/Vulkan-Headers/include",
})
local_platform_files()
@@ -33,7 +34,8 @@ project("xenia-gpu-shader-compiler")
"xenia-gpu",
"xenia-ui-vulkan",
})
defines({
includedirs({
project_root.."/third_party/Vulkan-Headers/include",
})
files({
"shader_compiler_main.cc",

85
src/xenia/gpu/render_target_cache.cc
View File

@@ -366,7 +366,7 @@ void RenderTargetCache::ClearCache() {
void RenderTargetCache::BeginFrame() { ResetAccumulatedRenderTargets(); }
bool RenderTargetCache::Update(bool is_rasterization_done,
uint32_t shader_writes_color_targets) {
uint32_t normalized_color_mask) {
const RegisterFile& regs = register_file();
bool interlock_barrier_only = GetPath() == Path::kPixelShaderInterlock;
@@ -419,9 +419,6 @@ bool RenderTargetCache::Update(bool is_rasterization_done,
}
}
uint32_t rts_remaining;
uint32_t rt_index;
// Get used render targets.
// [0] is depth / stencil where relevant, [1...4] is color.
// Depth / stencil testing / writing is before color in the pipeline.
@@ -432,7 +429,7 @@ bool RenderTargetCache::Update(bool is_rasterization_done,
uint32_t rts_are_64bpp = 0;
uint32_t color_rts_are_gamma = 0;
if (is_rasterization_done) {
auto rb_depthcontrol = regs.Get<reg::RB_DEPTHCONTROL>();
auto rb_depthcontrol = draw_util::GetDepthControlForCurrentEdramMode(regs);
if (rb_depthcontrol.z_enable || rb_depthcontrol.stencil_enable) {
depth_and_color_rts_used_bits |= 1;
auto rb_depth_info = regs.Get<reg::RB_DEPTH_INFO>();
@@ -445,50 +442,46 @@ bool RenderTargetCache::Update(bool is_rasterization_done,
resource_formats[0] =
interlock_barrier_only ? 0 : uint32_t(rb_depth_info.depth_format);
}
if (regs.Get<reg::RB_MODECONTROL>().edram_mode ==
xenos::ModeControl::kColorDepth) {
uint32_t rb_color_mask = regs[XE_GPU_REG_RB_COLOR_MASK].u32;
rts_remaining = shader_writes_color_targets;
while (xe::bit_scan_forward(rts_remaining, &rt_index)) {
rts_remaining &= ~(uint32_t(1) << rt_index);
auto color_info = regs.Get<reg::RB_COLOR_INFO>(
reg::RB_COLOR_INFO::rt_register_indices[rt_index]);
xenos::ColorRenderTargetFormat color_format =
regs.Get<reg::RB_COLOR_INFO>(
reg::RB_COLOR_INFO::rt_register_indices[rt_index])
.color_format;
if ((rb_color_mask >> (rt_index * 4)) &
((uint32_t(1) << xenos::GetColorRenderTargetFormatComponentCount(
color_format)) -
1)) {
uint32_t rt_bit_index = 1 + rt_index;
depth_and_color_rts_used_bits |= uint32_t(1) << rt_bit_index;
edram_bases[rt_bit_index] =
std::min(color_info.color_base, xenos::kEdramTileCount);
bool is_64bpp = xenos::IsColorRenderTargetFormat64bpp(color_format);
if (is_64bpp) {
rts_are_64bpp |= uint32_t(1) << rt_bit_index;
}
if (color_format == xenos::ColorRenderTargetFormat::k_8_8_8_8_GAMMA) {
color_rts_are_gamma |= uint32_t(1) << rt_index;
}
xenos::ColorRenderTargetFormat color_resource_format;
if (interlock_barrier_only) {
// Only changes in mapping between coordinates and addresses are
// interesting (along with access overlap between draw calls), thus
// only pixel size is relevant.
color_resource_format =
is_64bpp ? xenos::ColorRenderTargetFormat::k_16_16_16_16
: xenos::ColorRenderTargetFormat::k_8_8_8_8;
} else {
color_resource_format = GetColorResourceFormat(
xenos::GetStorageColorFormat(color_format));
}
resource_formats[rt_bit_index] = uint32_t(color_resource_format);
}
for (uint32_t i = 0; i < xenos::kMaxColorRenderTargets; ++i) {
if (!(normalized_color_mask & (uint32_t(0b1111) << (4 * i)))) {
continue;
}
auto color_info = regs.Get<reg::RB_COLOR_INFO>(
reg::RB_COLOR_INFO::rt_register_indices[i]);
uint32_t rt_bit_index = 1 + i;
depth_and_color_rts_used_bits |= uint32_t(1) << rt_bit_index;
edram_bases[rt_bit_index] =
std::min(color_info.color_base, xenos::kEdramTileCount);
xenos::ColorRenderTargetFormat color_format =
regs.Get<reg::RB_COLOR_INFO>(
reg::RB_COLOR_INFO::rt_register_indices[i])
.color_format;
bool is_64bpp = xenos::IsColorRenderTargetFormat64bpp(color_format);
if (is_64bpp) {
rts_are_64bpp |= uint32_t(1) << rt_bit_index;
}
if (color_format == xenos::ColorRenderTargetFormat::k_8_8_8_8_GAMMA) {
color_rts_are_gamma |= uint32_t(1) << i;
}
xenos::ColorRenderTargetFormat color_resource_format;
if (interlock_barrier_only) {
// Only changes in mapping between coordinates and addresses are
// interesting (along with access overlap between draw calls), thus only
// pixel size is relevant.
color_resource_format =
is_64bpp ? xenos::ColorRenderTargetFormat::k_16_16_16_16
: xenos::ColorRenderTargetFormat::k_8_8_8_8;
} else {
color_resource_format =
GetColorResourceFormat(xenos::GetStorageColorFormat(color_format));
}
resource_formats[rt_bit_index] = uint32_t(color_resource_format);
}
}
uint32_t rts_remaining;
uint32_t rt_index;
// Eliminate other bound render targets if their EDRAM base conflicts with
// another render target - it's an error in most host implementations to bind
// the same render target into multiple slots, also the behavior would be

2
src/xenia/gpu/render_target_cache.h
View File

@@ -215,7 +215,7 @@ class RenderTargetCache {
virtual void BeginFrame();
virtual bool Update(bool is_rasterization_done,
uint32_t shader_writes_color_targets);
uint32_t normalized_color_mask);
// Returns bits where 0 is whether a depth render target is currently bound on
// the host and 1... are whether the same applies to color render targets, and

3
src/xenia/gpu/vulkan/premake5.lua
View File

@@ -14,6 +14,9 @@ project("xenia-gpu-vulkan")
"xenia-ui-vulkan",
"xxhash",
})
includedirs({
project_root.."/third_party/Vulkan-Headers/include",
})
local_platform_files()
files({
"../shaders/bytecode/vulkan_spirv/*.h",