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[LINT] Linted files + Added lint job to CI

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This commit is contained in:
Gliniak
2024-03-12 08:59:10 +01:00
committed by Radosław Gliński
parent e8afad8f8a
commit b9061e6292
117 changed files with 1177 additions and 883 deletions
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27
src/xenia/gpu/command_processor.cc
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@@ -100,11 +100,14 @@ bool CommandProcessor::Initialize() {
}
worker_running_ = true;
worker_thread_ = kernel::object_ref<kernel::XHostThread>(
new kernel::XHostThread(kernel_state_, 128 * 1024, 0, [this]() {
WorkerThreadMain();
return 0;
}, kernel_state_->GetIdleProcess()));
worker_thread_ =
kernel::object_ref<kernel::XHostThread>(new kernel::XHostThread(
kernel_state_, 128 * 1024, 0,
[this]() {
WorkerThreadMain();
return 0;
},
kernel_state_->GetIdleProcess()));
worker_thread_->set_name("GPU Commands");
worker_thread_->Create();
@@ -270,7 +273,8 @@ void CommandProcessor::WorkerThreadMain() {
// TODO(benvanik): use reader->Read_update_freq_ and only issue after moving
// that many indices.
// Keep in mind that the gpu also updates the cpu-side copy if the write pointer and read pointer would be equal
// Keep in mind that the gpu also updates the cpu-side copy if the write
// pointer and read pointer would be equal
if (read_ptr_writeback_ptr_) {
xe::store_and_swap<uint32_t>(
memory_->TranslatePhysical(read_ptr_writeback_ptr_), read_ptr_index_);
@@ -360,9 +364,8 @@ void CommandProcessor::EnableReadPointerWriteBack(uint32_t ptr,
XE_NOINLINE XE_COLD void CommandProcessor::LogKickoffInitator(uint32_t value) {
cpu::backend::GuestPseudoStackTrace st;
if (logging::internal::ShouldLog(LogLevel::Debug) && kernel_state_->processor()
->backend()
->PopulatePseudoStacktrace(&st)) {
if (logging::internal::ShouldLog(LogLevel::Debug) &&
kernel_state_->processor()->backend()->PopulatePseudoStacktrace(&st)) {
logging::LoggerBatch<LogLevel::Debug> log_initiator{};
log_initiator("Updating read ptr to {}, initiator stacktrace below\n",
@@ -381,7 +384,7 @@ XE_NOINLINE XE_COLD void CommandProcessor::LogKickoffInitator(uint32_t value) {
}
void CommandProcessor::UpdateWritePointer(uint32_t value) {
XE_UNLIKELY_IF (cvars::log_ringbuffer_kickoff_initiator_bts) {
XE_UNLIKELY_IF(cvars::log_ringbuffer_kickoff_initiator_bts) {
LogKickoffInitator(value);
}
write_ptr_index_ = value;
@@ -390,7 +393,8 @@ void CommandProcessor::UpdateWritePointer(uint32_t value) {
void CommandProcessor::LogRegisterSet(uint32_t register_index, uint32_t value) {
#if XE_ENABLE_GPU_REG_WRITE_LOGGING == 1
if (cvars::log_guest_driven_gpu_register_written_values && logging::internal::ShouldLog(LogLevel::Debug)) {
if (cvars::log_guest_driven_gpu_register_written_values &&
logging::internal::ShouldLog(LogLevel::Debug)) {
const RegisterInfo* reginfo = RegisterFile::GetRegisterInfo(register_index);
if (!reginfo) {
@@ -734,7 +738,6 @@ void CommandProcessor::PrepareForWait() { trace_writer_.Flush(); }
void CommandProcessor::ReturnFromWait() {}
void CommandProcessor::InitializeTrace() {
// Write the initial register values, to be loaded directly into the
// RegisterFile since all registers, including those that may have side

1
src/xenia/gpu/command_processor.h
View File

@@ -225,7 +225,6 @@ class CommandProcessor {
virtual void PrepareForWait();
virtual void ReturnFromWait();
virtual void OnPrimaryBufferEnd() {}
#include "pm4_command_processor_declare.h"

8
src/xenia/gpu/d3d12/d3d12_command_processor.cc
View File

@@ -22,9 +22,9 @@
#include "xenia/gpu/d3d12/d3d12_shader.h"
#include "xenia/gpu/draw_util.h"
#include "xenia/gpu/gpu_flags.h"
#include "xenia/gpu/packet_disassembler.h"
#include "xenia/gpu/registers.h"
#include "xenia/gpu/xenos.h"
#include "xenia/gpu/packet_disassembler.h"
#include "xenia/ui/d3d12/d3d12_presenter.h"
#include "xenia/ui/d3d12/d3d12_util.h"
@@ -62,10 +62,9 @@ void D3D12SaveGPUSetting(D3D12GPUSetting setting, uint64_t value) {
break;
}
}
namespace d3d12 {
// Generated with `xb buildshaders`.
namespace shaders {
#include "xenia/gpu/shaders/bytecode/d3d12_5_1/apply_gamma_pwl_cs.h"
@@ -4992,7 +4991,8 @@ bool D3D12CommandProcessor::UpdateBindings_BindfulPath(
}
// Null SRV + UAV + EDRAM.
gpu_handle_shared_memory_uav_and_edram_ = view_gpu_handle;
ui::d3d12::util::CreateBufferRawSRV(provider.GetDevice(), view_cpu_handle, nullptr, 0);
ui::d3d12::util::CreateBufferRawSRV(provider.GetDevice(), view_cpu_handle,
nullptr, 0);
view_cpu_handle.ptr += descriptor_size_view;
view_gpu_handle.ptr += descriptor_size_view;
shared_memory_->WriteRawUAVDescriptor(view_cpu_handle);

13
src/xenia/gpu/d3d12/d3d12_command_processor.h
View File

@@ -231,13 +231,13 @@ class D3D12CommandProcessor final : public CommandProcessor {
XE_FORCEINLINE
void WriteRegisterForceinline(uint32_t index, uint32_t value);
void WriteRegister(uint32_t index, uint32_t value) override;
virtual void WriteRegistersFromMem(uint32_t start_index, uint32_t* base,
uint32_t num_registers) override;
/*helper functions for WriteRegistersFromMem*/
XE_FORCEINLINE
void WriteShaderConstantsFromMem(uint32_t start_index, uint32_t* base,
uint32_t num_registers);
uint32_t num_registers);
XE_FORCEINLINE
void WriteBoolLoopFromMem(uint32_t start_index, uint32_t* base,
uint32_t num_registers);
@@ -245,8 +245,9 @@ class D3D12CommandProcessor final : public CommandProcessor {
void WriteFetchFromMem(uint32_t start_index, uint32_t* base,
uint32_t num_registers);
void WritePossiblySpecialRegistersFromMem(uint32_t start_index, uint32_t* base,
uint32_t num_registers);
void WritePossiblySpecialRegistersFromMem(uint32_t start_index,
uint32_t* base,
uint32_t num_registers);
template <uint32_t register_lower_bound, uint32_t register_upper_bound>
XE_FORCEINLINE void WriteRegisterRangeFromMem_WithKnownBound(
uint32_t start_index, uint32_t* base, uint32_t num_registers);
@@ -262,8 +263,7 @@ class D3D12CommandProcessor final : public CommandProcessor {
uint32_t base,
uint32_t num_registers);
XE_NOINLINE
void WriteOneRegisterFromRing(uint32_t base,
uint32_t num_times);
void WriteOneRegisterFromRing(uint32_t base, uint32_t num_times);
XE_FORCEINLINE
void WriteALURangeFromRing(xe::RingBuffer* ring, uint32_t base,
@@ -795,7 +795,6 @@ class D3D12CommandProcessor final : public CommandProcessor {
draw_util::GetViewportInfoArgs previous_viewport_info_args_;
draw_util::ViewportInfo previous_viewport_info_;
std::atomic<bool> pix_capture_requested_ = false;
bool pix_capturing_;

8
src/xenia/gpu/d3d12/d3d12_texture_cache.cc
View File

@@ -672,11 +672,11 @@ uint32_t D3D12TextureCache::GetActiveTextureBindlessSRVIndex(
return descriptor_index;
}
void D3D12TextureCache::PrefetchSamplerParameters(
const D3D12Shader::SamplerBinding& binding) const {
const D3D12Shader::SamplerBinding& binding) const {
swcache::PrefetchL1(&register_file()[XE_GPU_REG_SHADER_CONSTANT_FETCH_00_0 +
binding.fetch_constant * 6]);
}
D3D12TextureCache::SamplerParameters D3D12TextureCache::GetSamplerParameters(
D3D12TextureCache::SamplerParameters D3D12TextureCache::GetSamplerParameters(
const D3D12Shader::SamplerBinding& binding) const {
const auto& regs = register_file();
const auto& fetch = regs.Get<xenos::xe_gpu_texture_fetch_t>(
@@ -703,8 +703,8 @@ void D3D12TextureCache::PrefetchSamplerParameters(
nullptr, nullptr, nullptr,
&mip_min_level, nullptr);
parameters.mip_min_level = mip_min_level;
//high cache miss count here, prefetch fetch earlier
// TODO(Triang3l): Disable filtering for texture formats not supporting it.
// high cache miss count here, prefetch fetch earlier
// TODO(Triang3l): Disable filtering for texture formats not supporting it.
xenos::AnisoFilter aniso_filter =
binding.aniso_filter == xenos::AnisoFilter::kUseFetchConst
? fetch.aniso_filter

9
src/xenia/gpu/d3d12/deferred_command_list.h
View File

@@ -18,8 +18,8 @@
#include "xenia/base/assert.h"
#include "xenia/base/literals.h"
#include "xenia/base/math.h"
#include "xenia/ui/d3d12/d3d12_api.h"
#include "xenia/base/memory.h"
#include "xenia/ui/d3d12/d3d12_api.h"
namespace xe {
namespace gpu {
namespace d3d12 {
@@ -30,9 +30,10 @@ class D3D12CommandProcessor;
class DeferredCommandList {
public:
static constexpr size_t MAX_SIZEOF_COMMANDLIST = 65536 * 128; //around 8 mb
static constexpr size_t MAX_SIZEOF_COMMANDLIST = 65536 * 128; // around 8 mb
/*
chrispy: upped from 1_MiB to 4_MiB, m:durandal hits frequent resizes in large open maps
chrispy: upped from 1_MiB to 4_MiB, m:durandal hits frequent resizes in
large open maps
*/
DeferredCommandList(const D3D12CommandProcessor& command_processor,
size_t initial_size_bytes = MAX_SIZEOF_COMMANDLIST);
@@ -566,7 +567,7 @@ class DeferredCommandList {
const D3D12CommandProcessor& command_processor_;
// uintmax_t to ensure uint64_t and pointer alignment of all structures.
//std::vector<uintmax_t> command_stream_;
// std::vector<uintmax_t> command_stream_;
FixedVMemVector<MAX_SIZEOF_COMMANDLIST> command_stream_;
};

8
src/xenia/gpu/draw_util.cc
View File

@@ -552,9 +552,8 @@ void GetHostViewportInfo(GetViewportInfoArgs* XE_RESTRICT args,
}
}
template <bool clamp_to_surface_pitch>
static inline
void GetScissorTmpl(const RegisterFile& XE_RESTRICT regs,
Scissor& XE_RESTRICT scissor_out) {
static inline void GetScissorTmpl(const RegisterFile& XE_RESTRICT regs,
Scissor& XE_RESTRICT scissor_out) {
#if XE_ARCH_AMD64 == 1
auto pa_sc_window_scissor_tl = regs.Get<reg::PA_SC_WINDOW_SCISSOR_TL>();
auto pa_sc_window_scissor_br = regs.Get<reg::PA_SC_WINDOW_SCISSOR_BR>();
@@ -623,8 +622,7 @@ void GetScissorTmpl(const RegisterFile& XE_RESTRICT regs,
// interlock-based custom RB implementations) and using conventional render
// targets, but padded to EDRAM tiles.
tmp1 = _mm_blend_epi16(
tmp1, _mm_min_epi32(tmp1, _mm_set1_epi32(surface_pitch)),
0b00110011);
tmp1, _mm_min_epi32(tmp1, _mm_set1_epi32(surface_pitch)), 0b00110011);
}
tmp1 = _mm_max_epi32(tmp1, _mm_setzero_si128());

76
src/xenia/gpu/graphics_system.cc
View File

@@ -25,10 +25,10 @@
#include "xenia/base/threading.h"
#include "xenia/gpu/command_processor.h"
#include "xenia/gpu/gpu_flags.h"
#include "xenia/kernel/kernel_state.h"
#include "xenia/ui/graphics_provider.h"
#include "xenia/ui/window.h"
#include "xenia/ui/windowed_app_context.h"
#include "xenia/kernel/kernel_state.h"
DEFINE_bool(
store_shaders, true,
"Store shaders persistently and load them when loading games to avoid "
@@ -102,43 +102,48 @@ X_STATUS GraphicsSystem::Setup(cpu::Processor* processor,
// 60hz vsync timer.
vsync_worker_running_ = true;
vsync_worker_thread_ = kernel::object_ref<kernel::XHostThread>(
new kernel::XHostThread(kernel_state_, 128 * 1024, 0, [this]() {
const double vsync_duration_d =
cvars::vsync
? std::max<double>(
5.0, 1000.0 / static_cast<double>(cvars::vsync_fps))
: 1.0;
uint64_t last_frame_time = Clock::QueryGuestTickCount();
// Sleep for 90% of the vblank duration, spin for 10%
const double duration_scalar = 0.90;
vsync_worker_thread_ =
kernel::object_ref<kernel::XHostThread>(new kernel::XHostThread(
kernel_state_, 128 * 1024, 0,
[this]() {
const double vsync_duration_d =
cvars::vsync
? std::max<double>(
5.0, 1000.0 / static_cast<double>(cvars::vsync_fps))
: 1.0;
uint64_t last_frame_time = Clock::QueryGuestTickCount();
// Sleep for 90% of the vblank duration, spin for 10%
const double duration_scalar = 0.90;
while (vsync_worker_running_) {
const uint64_t current_time = Clock::QueryGuestTickCount();
const uint64_t tick_freq = Clock::guest_tick_frequency();
const uint64_t time_delta = current_time - last_frame_time;
const double elapsed_d = static_cast<double>(time_delta) /
(static_cast<double>(tick_freq) / 1000.0);
if (elapsed_d >= vsync_duration_d) {
last_frame_time = current_time;
while (vsync_worker_running_) {
const uint64_t current_time = Clock::QueryGuestTickCount();
const uint64_t tick_freq = Clock::guest_tick_frequency();
const uint64_t time_delta = current_time - last_frame_time;
const double elapsed_d =
static_cast<double>(time_delta) /
(static_cast<double>(tick_freq) / 1000.0);
if (elapsed_d >= vsync_duration_d) {
last_frame_time = current_time;
// TODO(disjtqz): should recalculate the remaining time to a vblank
// after MarkVblank, no idea how long the guest code normally takes
MarkVblank();
if (cvars::vsync) {
const uint64_t estimated_nanoseconds = static_cast<uint64_t>(
(vsync_duration_d * 1000000.0) *
duration_scalar); // 1000 microseconds = 1 ms
// TODO(disjtqz): should recalculate the remaining time to a
// vblank after MarkVblank, no idea how long the guest code
// normally takes
MarkVblank();
if (cvars::vsync) {
const uint64_t estimated_nanoseconds = static_cast<uint64_t>(
(vsync_duration_d * 1000000.0) *
duration_scalar); // 1000 microseconds = 1 ms
threading::NanoSleep(estimated_nanoseconds);
threading::NanoSleep(estimated_nanoseconds);
}
}
if (!cvars::vsync) {
xe::threading::Sleep(std::chrono::milliseconds(1));
}
}
}
if (!cvars::vsync) {
xe::threading::Sleep(std::chrono::milliseconds(1));
}
}
return 0;
}, kernel_state->GetIdleProcess()));
return 0;
},
kernel_state->GetIdleProcess()));
// As we run vblank interrupts the debugger must be able to suspend us.
vsync_worker_thread_->set_can_debugger_suspend(true);
vsync_worker_thread_->set_name("GPU VSync");
@@ -267,7 +272,8 @@ void GraphicsSystem::SetInterruptCallback(uint32_t callback,
}
void GraphicsSystem::DispatchInterruptCallback(uint32_t source, uint32_t cpu) {
kernel_state()->EmulateCPInterruptDPC(interrupt_callback_,interrupt_callback_data_, source, cpu);
kernel_state()->EmulateCPInterruptDPC(interrupt_callback_,
interrupt_callback_data_, source, cpu);
}
void GraphicsSystem::MarkVblank() {

77
src/xenia/gpu/pm4_command_processor_declare.h
View File

@@ -1,12 +1,11 @@
#if defined(OVERRIDING_BASE_CMDPROCESSOR)
#define PM4_OVERRIDE override
#define PM4_OVERRIDE override
#else
#define PM4_OVERRIDE
#endif
void ExecuteIndirectBuffer(uint32_t ptr,
uint32_t count) XE_RESTRICT;
void ExecuteIndirectBuffer(uint32_t ptr, uint32_t count) XE_RESTRICT;
virtual uint32_t ExecutePrimaryBuffer(uint32_t start_index, uint32_t end_index)
XE_RESTRICT PM4_OVERRIDE;
virtual bool ExecutePacket() PM4_OVERRIDE;
@@ -18,91 +17,77 @@ protected:
XE_NOINLINE
void DisassembleCurrentPacket() XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType0( uint32_t packet) XE_RESTRICT;
bool ExecutePacketType0(uint32_t packet) XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType1( uint32_t packet) XE_RESTRICT;
bool ExecutePacketType1(uint32_t packet) XE_RESTRICT;
bool ExecutePacketType2( uint32_t packet) XE_RESTRICT;
bool ExecutePacketType2(uint32_t packet) XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType3( uint32_t packet) XE_RESTRICT;
bool ExecutePacketType3(uint32_t packet) XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType3_ME_INIT( uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_NOP( uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_ME_INIT(uint32_t packet, uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_NOP(uint32_t packet, uint32_t count) XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType3_INTERRUPT( uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_INTERRUPT(uint32_t packet, uint32_t count) XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType3_XE_SWAP( uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_XE_SWAP(uint32_t packet, uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_INDIRECT_BUFFER( uint32_t packet,
bool ExecutePacketType3_INDIRECT_BUFFER(uint32_t packet,
uint32_t count) XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType3_WAIT_REG_MEM( uint32_t packet,
bool ExecutePacketType3_WAIT_REG_MEM(uint32_t packet,
uint32_t count) XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType3_REG_RMW( uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_REG_RMW(uint32_t packet, uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_REG_TO_MEM( uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_REG_TO_MEM(uint32_t packet, uint32_t count) XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType3_MEM_WRITE( uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_MEM_WRITE(uint32_t packet, uint32_t count) XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType3_COND_WRITE( uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_COND_WRITE(uint32_t packet, uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_EVENT_WRITE( uint32_t packet,
bool ExecutePacketType3_EVENT_WRITE(uint32_t packet,
uint32_t count) XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType3_EVENT_WRITE_SHD( uint32_t packet,
bool ExecutePacketType3_EVENT_WRITE_SHD(uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_EVENT_WRITE_EXT( uint32_t packet,
bool ExecutePacketType3_EVENT_WRITE_EXT(uint32_t packet,
uint32_t count) XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType3_EVENT_WRITE_ZPD( uint32_t packet,
bool ExecutePacketType3_EVENT_WRITE_ZPD(uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3Draw( uint32_t packet,
const char* opcode_name,
bool ExecutePacketType3Draw(uint32_t packet, const char* opcode_name,
uint32_t viz_query_condition,
uint32_t count_remaining) XE_RESTRICT;
bool ExecutePacketType3_DRAW_INDX( uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_DRAW_INDX(uint32_t packet, uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_DRAW_INDX_2( uint32_t packet,
bool ExecutePacketType3_DRAW_INDX_2(uint32_t packet,
uint32_t count) XE_RESTRICT;
XE_FORCEINLINE
bool ExecutePacketType3_SET_CONSTANT( uint32_t packet,
bool ExecutePacketType3_SET_CONSTANT(uint32_t packet,
uint32_t count) XE_RESTRICT;
XE_NOINLINE
bool ExecutePacketType3_SET_CONSTANT2( uint32_t packet,
bool ExecutePacketType3_SET_CONSTANT2(uint32_t packet,
uint32_t count) XE_RESTRICT;
XE_FORCEINLINE
bool ExecutePacketType3_LOAD_ALU_CONSTANT( uint32_t packet,
bool ExecutePacketType3_LOAD_ALU_CONSTANT(uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_SET_SHADER_CONSTANTS(
uint32_t packet,
bool ExecutePacketType3_SET_SHADER_CONSTANTS(uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_IM_LOAD( uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_IM_LOAD(uint32_t packet, uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_IM_LOAD_IMMEDIATE( uint32_t packet,
bool ExecutePacketType3_IM_LOAD_IMMEDIATE(uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_INVALIDATE_STATE( uint32_t packet,
bool ExecutePacketType3_INVALIDATE_STATE(uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_VIZ_QUERY( uint32_t packet,
uint32_t count) XE_RESTRICT;
bool ExecutePacketType3_VIZ_QUERY(uint32_t packet, uint32_t count) XE_RESTRICT;
XE_FORCEINLINE
void WriteEventInitiator(uint32_t value) XE_RESTRICT;

27
src/xenia/gpu/pm4_command_processor_implement.h
View File

@@ -683,13 +683,12 @@ bool COMMAND_PROCESSOR::ExecutePacketType3_INDIRECT_BUFFER(
to 54 bytes
*/
static bool MatchValueAndRef(uint32_t value, uint32_t ref, uint32_t wait_info) {
// smaller code is generated than the #else path, although whether it is faster
// i do not know. i don't think games do an enormous number of cond_write
// though, so we have picked
// the path with the smaller codegen.
// we do technically have more instructions executed vs the switch case method,
// but we have no mispredicts and most of our instructions are 0.25/0.3
// throughput
// smaller code is generated than the #else path, although whether it is
// faster i do not know. i don't think games do an enormous number of
// cond_write though, so we have picked the path with the smaller codegen. we
// do technically have more instructions executed vs the switch case method,
// but we have no mispredicts and most of our instructions are 0.25/0.3
// throughput
return ((((value < ref) << 1) | ((value <= ref) << 2) |
((value == ref) << 3) | ((value != ref) << 4) |
((value >= ref) << 5) | ((value > ref) << 6) | (1 << 7)) >>
@@ -899,13 +898,17 @@ bool COMMAND_PROCESSOR::ExecutePacketType3_EVENT_WRITE_SHD(
data_value = GpuSwap(data_value, endianness);
uint8_t* write_destination = memory_->TranslatePhysical(address);
if (address > 0x1FFFFFFF) {
uint32_t writeback_base = register_file_->values[XE_GPU_REG_WRITEBACK_BASE].u32;
uint32_t writeback_size = register_file_->values[XE_GPU_REG_WRITEBACK_SIZE].u32;
uint32_t writeback_base =
register_file_->values[XE_GPU_REG_WRITEBACK_BASE].u32;
uint32_t writeback_size =
register_file_->values[XE_GPU_REG_WRITEBACK_SIZE].u32;
uint32_t writeback_offset = address - writeback_base;
//check whether the guest has written writeback base. if they haven't, skip the offset check
// check whether the guest has written writeback base. if they haven't, skip
// the offset check
if (writeback_base != 0 && writeback_offset < writeback_size) {
write_destination = memory_->TranslateVirtual(0x7F000000 + writeback_offset);
}
write_destination =
memory_->TranslateVirtual(0x7F000000 + writeback_offset);
}
}
xe::store(write_destination, data_value);
trace_writer_.WriteMemoryWrite(CpuToGpu(address), 4);

3
src/xenia/gpu/primitive_processor.h
View File

@@ -883,8 +883,7 @@ class PrimitiveProcessor {
// Must be called in a global critical region.
void UpdateCacheBucketsNonEmptyL2(
uint32_t bucket_index_div_64,
[[maybe_unused]] const global_unique_lock_type&
global_lock) {
[[maybe_unused]] const global_unique_lock_type& global_lock) {
uint64_t& cache_buckets_non_empty_l2_ref =
cache_buckets_non_empty_l2_[bucket_index_div_64 >> 6];
uint64_t cache_buckets_non_empty_l2_bit = uint64_t(1)

45
src/xenia/gpu/register_table.inc
View File

@@ -13,7 +13,7 @@
// Almost all of these values are taken directly from:
// https://github.com/freedreno/amd-gpu/blob/master/include/reg/yamato/22/yamato_offset.h
//#define XE_GPU_REGISTER(index, type, name)
// #define XE_GPU_REGISTER(index, type, name)
XE_GPU_REGISTER(0x0048, kDword, BIF_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0049, kDword, BIF_PERFCOUNTER0_HI)
@@ -36,35 +36,36 @@ XE_GPU_REGISTER(0x0398, kDword, RBBM_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0399, kDword, RBBM_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x039A, kDword, RBBM_PERFCOUNTER1_HI)
//XAM reads this directly and stores it to a struct, have not tracked where it goes from there
//PM4 command PM4_MEM_WRITE_CNTR is supposed to write this to memory
//XE_GPU_REGISTER(0x44b, kDword,CP_PROG_COUNTER )
// XAM reads this directly and stores it to a struct, have not tracked where it
// goes from there PM4 command PM4_MEM_WRITE_CNTR is supposed to write this to
// memory XE_GPU_REGISTER(0x44b, kDword,CP_PROG_COUNTER )
XE_GPU_REGISTER(0x045E, kDword, CALLBACK_ACK)
XE_GPU_REGISTER(0x0578, kDword, SCRATCH_REG0) // interrupt sync
XE_GPU_REGISTER(0x0579, kDword, SCRATCH_REG1) // present interval
XE_GPU_REGISTER(0x057A, kDword, SCRATCH_REG2)
XE_GPU_REGISTER(0x057B, kDword, SCRATCH_REG3)
XE_GPU_REGISTER(0x057C, kDword, SCRATCH_REG4) //originally this was named CALLBACK_ADDRESS, but that didnt make sense
XE_GPU_REGISTER(0x057C, kDword,
SCRATCH_REG4) // originally this was named CALLBACK_ADDRESS,
// but that didnt make sense
XE_GPU_REGISTER(0x057D, kDword, SCRATCH_REG5)
XE_GPU_REGISTER(0x057E, kDword, SCRATCH_REG6)
XE_GPU_REGISTER(0x057F, kDword, SCRATCH_REG7)
XE_GPU_REGISTER(0x05C8, kDword, WAIT_UNTIL)
//src is flash_xam.xex, i've seen it used by the kernel and aurora
//seems to have a negative value while the gpu is busy
//XE_GPU_REGISTER(0x05D0, kDword, RBBM_STATUS)
// src is flash_xam.xex, i've seen it used by the kernel and aurora
// seems to have a negative value while the gpu is busy
// XE_GPU_REGISTER(0x05D0, kDword, RBBM_STATUS)
// update count = 6 bit field, bits 8- 14
// there are several other fields here, they have an unknown purpose
// XE_GPU_REGISTER(0x704, kDword, CP_RB_CNTL)
//update count = 6 bit field, bits 8- 14
//there are several other fields here, they have an unknown purpose
//XE_GPU_REGISTER(0x704, kDword, CP_RB_CNTL)
//address must be 4 byte aligned
//low 2 bits encode two different fields?
//xboxkrnl just does addr |2 when assigning
//XE_GPU_REGISTER(0x70C, kDword, CP_RB_RPTR_ADDR)
// address must be 4 byte aligned
// low 2 bits encode two different fields?
// xboxkrnl just does addr |2 when assigning
// XE_GPU_REGISTER(0x70C, kDword, CP_RB_RPTR_ADDR)
XE_GPU_REGISTER(0x0815, kDword, MC0_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0816, kDword, MC0_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0817, kDword, MC0_PERFCOUNTER0_LOW)
@@ -72,13 +73,13 @@ XE_GPU_REGISTER(0x0855, kDword, MC1_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0856, kDword, MC1_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0857, kDword, MC1_PERFCOUNTER0_LOW)
//base GPU virtual address of the xps region. Most guests write 0xC0100000 here
// base GPU virtual address of the xps region. Most guests write 0xC0100000 here
XE_GPU_REGISTER(0x0A02, kDword, XPS_BASE)
//will usually be set higher, but is effectively 0x700000 bytes long
// will usually be set higher, but is effectively 0x700000 bytes long
XE_GPU_REGISTER(0x0A03, kDword, XPS_SIZE)
//usually 0xC0000000
// usually 0xC0000000
XE_GPU_REGISTER(0x0A04, kDword, WRITEBACK_BASE)
//usually 0x0100000
// usually 0x0100000
XE_GPU_REGISTER(0x0A05, kDword, WRITEBACK_SIZE)
XE_GPU_REGISTER(0x0A18, kDword, MH_PERFCOUNTER0_SELECT)
@@ -279,8 +280,8 @@ XE_GPU_REGISTER(0x0F0C, kDword, BC_PERFCOUNTER2_LOW)
XE_GPU_REGISTER(0x0F0D, kDword, BC_PERFCOUNTER2_HI)
XE_GPU_REGISTER(0x0F0E, kDword, BC_PERFCOUNTER3_LOW)
XE_GPU_REGISTER(0x0F0F, kDword, BC_PERFCOUNTER3_HI)
//src is flash_xam.xex
//XE_GPU_REGISTER(0x0F12, RB_SIDEBAND_DATA,
// src is flash_xam.xex
// XE_GPU_REGISTER(0x0F12, RB_SIDEBAND_DATA,
XE_GPU_REGISTER(0x1004, kDword, HZ_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x1005, kDword, HZ_PERFCOUNTER0_HI)

3
src/xenia/gpu/render_target_cache.h
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@@ -231,8 +231,7 @@ class RenderTargetCache {
: register_file_(register_file),
draw_resolution_scale_x_(draw_resolution_scale_x),
draw_resolution_scale_y_(draw_resolution_scale_y),
draw_extent_estimator_(register_file, memory, trace_writer)
{
draw_extent_estimator_(register_file, memory, trace_writer) {
assert_not_zero(draw_resolution_scale_x);
assert_not_zero(draw_resolution_scale_y);
}

8
src/xenia/gpu/shared_memory.h
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@@ -209,10 +209,10 @@ class SharedMemory {
uint64_t valid_and_gpu_resolved;
};
//chrispy: todo, systempageflagsblock should be 3 different arrays
// Flags for each 64 system pages, interleaved as blocks, so bit scan can be
// used to quickly extract ranges.
// std::vector<SystemPageFlagsBlock> system_page_flags_;
// chrispy: todo, systempageflagsblock should be 3 different arrays
// Flags for each 64 system pages, interleaved as blocks, so bit scan can be
// used to quickly extract ranges.
// std::vector<SystemPageFlagsBlock> system_page_flags_;
uint64_t *system_page_flags_valid_ = nullptr,
*system_page_flags_valid_and_gpu_written_ = nullptr,

3
src/xenia/gpu/texture_cache.h
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@@ -108,7 +108,8 @@ class TextureCache {
// generate a mask of all bits from before the first index, and xor it with
// all bits before the last index this produces a mask covering only the
// bits between first and last
uint32_t res = ((1U << first_index) - 1) ^ static_cast<uint32_t>((1ULL << (last_index + 1)) - 1ULL);
uint32_t res = ((1U << first_index) - 1) ^
static_cast<uint32_t>((1ULL << (last_index + 1)) - 1ULL);
// todo: check that this is right
texture_bindings_in_sync_ &= ~res;

126
src/xenia/gpu/texture_info_formats.inl
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@@ -1,64 +1,64 @@
FORMAT_INFO(k_1_REVERSE, kUncompressed, 1, 1, 1),
FORMAT_INFO(k_1, kUncompressed, 1, 1, 1),
FORMAT_INFO(k_8, kResolvable, 1, 1, 8),
FORMAT_INFO(k_1_5_5_5, kResolvable, 1, 1, 16),
FORMAT_INFO(k_5_6_5, kResolvable, 1, 1, 16),
FORMAT_INFO(k_6_5_5, kResolvable, 1, 1, 16),
FORMAT_INFO(k_8_8_8_8, kResolvable, 1, 1, 32),
FORMAT_INFO(k_2_10_10_10, kResolvable, 1, 1, 32),
FORMAT_INFO(k_8_A, kResolvable, 1, 1, 8),
FORMAT_INFO(k_8_B, kResolvable, 1, 1, 8),
FORMAT_INFO(k_8_8, kResolvable, 1, 1, 16),
FORMAT_INFO(k_Cr_Y1_Cb_Y0_REP, kCompressed, 2, 1, 16),
FORMAT_INFO(k_Y1_Cr_Y0_Cb_REP, kCompressed, 2, 1, 16),
FORMAT_INFO(k_16_16_EDRAM, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_8_8_8_8_A, kResolvable, 1, 1, 32),
FORMAT_INFO(k_4_4_4_4, kResolvable, 1, 1, 16),
FORMAT_INFO(k_10_11_11, kResolvable, 1, 1, 32),
FORMAT_INFO(k_11_11_10, kResolvable, 1, 1, 32),
FORMAT_INFO(k_DXT1, kCompressed, 4, 4, 4),
FORMAT_INFO(k_DXT2_3, kCompressed, 4, 4, 8),
FORMAT_INFO(k_DXT4_5, kCompressed, 4, 4, 8),
FORMAT_INFO(k_16_16_16_16_EDRAM, kUncompressed, 1, 1, 64),
FORMAT_INFO(k_24_8, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_24_8_FLOAT, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_16, kResolvable, 1, 1, 16),
FORMAT_INFO(k_16_16, kResolvable, 1, 1, 32),
FORMAT_INFO(k_16_16_16_16, kResolvable, 1, 1, 64),
FORMAT_INFO(k_16_EXPAND, kUncompressed, 1, 1, 16),
FORMAT_INFO(k_16_16_EXPAND, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_16_16_16_16_EXPAND, kUncompressed, 1, 1, 64),
FORMAT_INFO(k_16_FLOAT, kResolvable, 1, 1, 16),
FORMAT_INFO(k_16_16_FLOAT, kResolvable, 1, 1, 32),
FORMAT_INFO(k_16_16_16_16_FLOAT, kResolvable, 1, 1, 64),
FORMAT_INFO(k_32, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_32_32, kUncompressed, 1, 1, 64),
FORMAT_INFO(k_32_32_32_32, kUncompressed, 1, 1, 128),
FORMAT_INFO(k_32_FLOAT, kResolvable, 1, 1, 32),
FORMAT_INFO(k_32_32_FLOAT, kResolvable, 1, 1, 64),
FORMAT_INFO(k_32_32_32_32_FLOAT, kResolvable, 1, 1, 128),
FORMAT_INFO(k_32_AS_8, kCompressed, 4, 1, 8),
FORMAT_INFO(k_32_AS_8_8, kCompressed, 2, 1, 16),
FORMAT_INFO(k_16_MPEG, kUncompressed, 1, 1, 16),
FORMAT_INFO(k_16_16_MPEG, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_8_INTERLACED, kUncompressed, 1, 1, 8),
FORMAT_INFO(k_32_AS_8_INTERLACED, kCompressed, 4, 1, 8),
FORMAT_INFO(k_32_AS_8_8_INTERLACED, kCompressed, 1, 1, 16),
FORMAT_INFO(k_16_INTERLACED, kUncompressed, 1, 1, 16),
FORMAT_INFO(k_16_MPEG_INTERLACED, kUncompressed, 1, 1, 16),
FORMAT_INFO(k_16_16_MPEG_INTERLACED, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_DXN, kCompressed, 4, 4, 8),
FORMAT_INFO(k_8_8_8_8_AS_16_16_16_16, kResolvable, 1, 1, 32),
FORMAT_INFO(k_DXT1_AS_16_16_16_16, kCompressed, 4, 4, 4),
FORMAT_INFO(k_DXT2_3_AS_16_16_16_16, kCompressed, 4, 4, 8),
FORMAT_INFO(k_DXT4_5_AS_16_16_16_16, kCompressed, 4, 4, 8),
FORMAT_INFO(k_2_10_10_10_AS_16_16_16_16, kResolvable, 1, 1, 32),
FORMAT_INFO(k_10_11_11_AS_16_16_16_16, kResolvable, 1, 1, 32),
FORMAT_INFO(k_11_11_10_AS_16_16_16_16, kResolvable, 1, 1, 32),
FORMAT_INFO(k_32_32_32_FLOAT, kUncompressed, 1, 1, 96),
FORMAT_INFO(k_DXT3A, kCompressed, 4, 4, 4),
FORMAT_INFO(k_DXT5A, kCompressed, 4, 4, 4),
FORMAT_INFO(k_CTX1, kCompressed, 4, 4, 4),
FORMAT_INFO(k_DXT3A_AS_1_1_1_1, kCompressed, 4, 4, 4),
FORMAT_INFO(k_8_8_8_8_GAMMA_EDRAM, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_2_10_10_10_FLOAT_EDRAM, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_1, kUncompressed, 1, 1, 1),
FORMAT_INFO(k_8, kResolvable, 1, 1, 8),
FORMAT_INFO(k_1_5_5_5, kResolvable, 1, 1, 16),
FORMAT_INFO(k_5_6_5, kResolvable, 1, 1, 16),
FORMAT_INFO(k_6_5_5, kResolvable, 1, 1, 16),
FORMAT_INFO(k_8_8_8_8, kResolvable, 1, 1, 32),
FORMAT_INFO(k_2_10_10_10, kResolvable, 1, 1, 32),
FORMAT_INFO(k_8_A, kResolvable, 1, 1, 8),
FORMAT_INFO(k_8_B, kResolvable, 1, 1, 8),
FORMAT_INFO(k_8_8, kResolvable, 1, 1, 16),
FORMAT_INFO(k_Cr_Y1_Cb_Y0_REP, kCompressed, 2, 1, 16),
FORMAT_INFO(k_Y1_Cr_Y0_Cb_REP, kCompressed, 2, 1, 16),
FORMAT_INFO(k_16_16_EDRAM, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_8_8_8_8_A, kResolvable, 1, 1, 32),
FORMAT_INFO(k_4_4_4_4, kResolvable, 1, 1, 16),
FORMAT_INFO(k_10_11_11, kResolvable, 1, 1, 32),
FORMAT_INFO(k_11_11_10, kResolvable, 1, 1, 32),
FORMAT_INFO(k_DXT1, kCompressed, 4, 4, 4),
FORMAT_INFO(k_DXT2_3, kCompressed, 4, 4, 8),
FORMAT_INFO(k_DXT4_5, kCompressed, 4, 4, 8),
FORMAT_INFO(k_16_16_16_16_EDRAM, kUncompressed, 1, 1, 64),
FORMAT_INFO(k_24_8, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_24_8_FLOAT, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_16, kResolvable, 1, 1, 16),
FORMAT_INFO(k_16_16, kResolvable, 1, 1, 32),
FORMAT_INFO(k_16_16_16_16, kResolvable, 1, 1, 64),
FORMAT_INFO(k_16_EXPAND, kUncompressed, 1, 1, 16),
FORMAT_INFO(k_16_16_EXPAND, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_16_16_16_16_EXPAND, kUncompressed, 1, 1, 64),
FORMAT_INFO(k_16_FLOAT, kResolvable, 1, 1, 16),
FORMAT_INFO(k_16_16_FLOAT, kResolvable, 1, 1, 32),
FORMAT_INFO(k_16_16_16_16_FLOAT, kResolvable, 1, 1, 64),
FORMAT_INFO(k_32, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_32_32, kUncompressed, 1, 1, 64),
FORMAT_INFO(k_32_32_32_32, kUncompressed, 1, 1, 128),
FORMAT_INFO(k_32_FLOAT, kResolvable, 1, 1, 32),
FORMAT_INFO(k_32_32_FLOAT, kResolvable, 1, 1, 64),
FORMAT_INFO(k_32_32_32_32_FLOAT, kResolvable, 1, 1, 128),
FORMAT_INFO(k_32_AS_8, kCompressed, 4, 1, 8),
FORMAT_INFO(k_32_AS_8_8, kCompressed, 2, 1, 16),
FORMAT_INFO(k_16_MPEG, kUncompressed, 1, 1, 16),
FORMAT_INFO(k_16_16_MPEG, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_8_INTERLACED, kUncompressed, 1, 1, 8),
FORMAT_INFO(k_32_AS_8_INTERLACED, kCompressed, 4, 1, 8),
FORMAT_INFO(k_32_AS_8_8_INTERLACED, kCompressed, 1, 1, 16),
FORMAT_INFO(k_16_INTERLACED, kUncompressed, 1, 1, 16),
FORMAT_INFO(k_16_MPEG_INTERLACED, kUncompressed, 1, 1, 16),
FORMAT_INFO(k_16_16_MPEG_INTERLACED, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_DXN, kCompressed, 4, 4, 8),
FORMAT_INFO(k_8_8_8_8_AS_16_16_16_16, kResolvable, 1, 1, 32),
FORMAT_INFO(k_DXT1_AS_16_16_16_16, kCompressed, 4, 4, 4),
FORMAT_INFO(k_DXT2_3_AS_16_16_16_16, kCompressed, 4, 4, 8),
FORMAT_INFO(k_DXT4_5_AS_16_16_16_16, kCompressed, 4, 4, 8),
FORMAT_INFO(k_2_10_10_10_AS_16_16_16_16, kResolvable, 1, 1, 32),
FORMAT_INFO(k_10_11_11_AS_16_16_16_16, kResolvable, 1, 1, 32),
FORMAT_INFO(k_11_11_10_AS_16_16_16_16, kResolvable, 1, 1, 32),
FORMAT_INFO(k_32_32_32_FLOAT, kUncompressed, 1, 1, 96),
FORMAT_INFO(k_DXT3A, kCompressed, 4, 4, 4),
FORMAT_INFO(k_DXT5A, kCompressed, 4, 4, 4),
FORMAT_INFO(k_CTX1, kCompressed, 4, 4, 4),
FORMAT_INFO(k_DXT3A_AS_1_1_1_1, kCompressed, 4, 4, 4),
FORMAT_INFO(k_8_8_8_8_GAMMA_EDRAM, kUncompressed, 1, 1, 32),
FORMAT_INFO(k_2_10_10_10_FLOAT_EDRAM, kUncompressed, 1, 1, 32),

2
src/xenia/gpu/vulkan/vulkan_command_processor.cc
View File

@@ -24,6 +24,7 @@
#include "xenia/base/profiling.h"
#include "xenia/gpu/draw_util.h"
#include "xenia/gpu/gpu_flags.h"
#include "xenia/gpu/packet_disassembler.h"
#include "xenia/gpu/registers.h"
#include "xenia/gpu/shader.h"
#include "xenia/gpu/spirv_shader_translator.h"
@@ -32,7 +33,6 @@
#include "xenia/gpu/vulkan/vulkan_shader.h"
#include "xenia/gpu/vulkan/vulkan_shared_memory.h"
#include "xenia/gpu/xenos.h"
#include "xenia/gpu/packet_disassembler.h"
#include "xenia/kernel/kernel_state.h"
#include "xenia/kernel/user_module.h"
#include "xenia/ui/vulkan/vulkan_presenter.h"

6
src/xenia/gpu/xenos.h
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@@ -10,10 +10,8 @@
#ifndef XENIA_GPU_XENOS_H_
#define XENIA_GPU_XENOS_H_
#include "xenia/base/memory.h"
#include "xenia/base/math.h"
#include "xenia/base/memory.h"
namespace xe {
namespace gpu {
@@ -421,7 +419,7 @@ float Float7e3To32(uint32_t f10);
// floating-point number.
// Converts an IEEE-754 32-bit floating-point number to Xenos floating-point
// depth, rounding to the nearest even or towards zero.
XE_NOALIAS
XE_NOALIAS
uint32_t Float32To20e4(float f32, bool round_to_nearest_even) noexcept;
// Converts Xenos floating-point depth in bits 0:23 (not clamping) to an
// IEEE-754 32-bit floating-point number.