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[LINT] Linted files + Added lint job to CI

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This commit is contained in:
Gliniak
2024-03-12 08:59:10 +01:00
committed by Radosław Gliński
parent e8afad8f8a
commit b9061e6292
117 changed files with 1177 additions and 883 deletions
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8
src/xenia/gpu/d3d12/d3d12_command_processor.cc
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@@ -22,9 +22,9 @@
#include "xenia/gpu/d3d12/d3d12_shader.h"
#include "xenia/gpu/draw_util.h"
#include "xenia/gpu/gpu_flags.h"
#include "xenia/gpu/packet_disassembler.h"
#include "xenia/gpu/registers.h"
#include "xenia/gpu/xenos.h"
#include "xenia/gpu/packet_disassembler.h"
#include "xenia/ui/d3d12/d3d12_presenter.h"
#include "xenia/ui/d3d12/d3d12_util.h"
@@ -62,10 +62,9 @@ void D3D12SaveGPUSetting(D3D12GPUSetting setting, uint64_t value) {
break;
}
}
namespace d3d12 {
// Generated with `xb buildshaders`.
namespace shaders {
#include "xenia/gpu/shaders/bytecode/d3d12_5_1/apply_gamma_pwl_cs.h"
@@ -4992,7 +4991,8 @@ bool D3D12CommandProcessor::UpdateBindings_BindfulPath(
}
// Null SRV + UAV + EDRAM.
gpu_handle_shared_memory_uav_and_edram_ = view_gpu_handle;
ui::d3d12::util::CreateBufferRawSRV(provider.GetDevice(), view_cpu_handle, nullptr, 0);
ui::d3d12::util::CreateBufferRawSRV(provider.GetDevice(), view_cpu_handle,
nullptr, 0);
view_cpu_handle.ptr += descriptor_size_view;
view_gpu_handle.ptr += descriptor_size_view;
shared_memory_->WriteRawUAVDescriptor(view_cpu_handle);

13
src/xenia/gpu/d3d12/d3d12_command_processor.h
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@@ -231,13 +231,13 @@ class D3D12CommandProcessor final : public CommandProcessor {
XE_FORCEINLINE
void WriteRegisterForceinline(uint32_t index, uint32_t value);
void WriteRegister(uint32_t index, uint32_t value) override;
virtual void WriteRegistersFromMem(uint32_t start_index, uint32_t* base,
uint32_t num_registers) override;
/*helper functions for WriteRegistersFromMem*/
XE_FORCEINLINE
void WriteShaderConstantsFromMem(uint32_t start_index, uint32_t* base,
uint32_t num_registers);
uint32_t num_registers);
XE_FORCEINLINE
void WriteBoolLoopFromMem(uint32_t start_index, uint32_t* base,
uint32_t num_registers);
@@ -245,8 +245,9 @@ class D3D12CommandProcessor final : public CommandProcessor {
void WriteFetchFromMem(uint32_t start_index, uint32_t* base,
uint32_t num_registers);
void WritePossiblySpecialRegistersFromMem(uint32_t start_index, uint32_t* base,
uint32_t num_registers);
void WritePossiblySpecialRegistersFromMem(uint32_t start_index,
uint32_t* base,
uint32_t num_registers);
template <uint32_t register_lower_bound, uint32_t register_upper_bound>
XE_FORCEINLINE void WriteRegisterRangeFromMem_WithKnownBound(
uint32_t start_index, uint32_t* base, uint32_t num_registers);
@@ -262,8 +263,7 @@ class D3D12CommandProcessor final : public CommandProcessor {
uint32_t base,
uint32_t num_registers);
XE_NOINLINE
void WriteOneRegisterFromRing(uint32_t base,
uint32_t num_times);
void WriteOneRegisterFromRing(uint32_t base, uint32_t num_times);
XE_FORCEINLINE
void WriteALURangeFromRing(xe::RingBuffer* ring, uint32_t base,
@@ -795,7 +795,6 @@ class D3D12CommandProcessor final : public CommandProcessor {
draw_util::GetViewportInfoArgs previous_viewport_info_args_;
draw_util::ViewportInfo previous_viewport_info_;
std::atomic<bool> pix_capture_requested_ = false;
bool pix_capturing_;

8
src/xenia/gpu/d3d12/d3d12_texture_cache.cc
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@@ -672,11 +672,11 @@ uint32_t D3D12TextureCache::GetActiveTextureBindlessSRVIndex(
return descriptor_index;
}
void D3D12TextureCache::PrefetchSamplerParameters(
const D3D12Shader::SamplerBinding& binding) const {
const D3D12Shader::SamplerBinding& binding) const {
swcache::PrefetchL1(&register_file()[XE_GPU_REG_SHADER_CONSTANT_FETCH_00_0 +
binding.fetch_constant * 6]);
}
D3D12TextureCache::SamplerParameters D3D12TextureCache::GetSamplerParameters(
D3D12TextureCache::SamplerParameters D3D12TextureCache::GetSamplerParameters(
const D3D12Shader::SamplerBinding& binding) const {
const auto& regs = register_file();
const auto& fetch = regs.Get<xenos::xe_gpu_texture_fetch_t>(
@@ -703,8 +703,8 @@ void D3D12TextureCache::PrefetchSamplerParameters(
nullptr, nullptr, nullptr,
&mip_min_level, nullptr);
parameters.mip_min_level = mip_min_level;
//high cache miss count here, prefetch fetch earlier
// TODO(Triang3l): Disable filtering for texture formats not supporting it.
// high cache miss count here, prefetch fetch earlier
// TODO(Triang3l): Disable filtering for texture formats not supporting it.
xenos::AnisoFilter aniso_filter =
binding.aniso_filter == xenos::AnisoFilter::kUseFetchConst
? fetch.aniso_filter

9
src/xenia/gpu/d3d12/deferred_command_list.h
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@@ -18,8 +18,8 @@
#include "xenia/base/assert.h"
#include "xenia/base/literals.h"
#include "xenia/base/math.h"
#include "xenia/ui/d3d12/d3d12_api.h"
#include "xenia/base/memory.h"
#include "xenia/ui/d3d12/d3d12_api.h"
namespace xe {
namespace gpu {
namespace d3d12 {
@@ -30,9 +30,10 @@ class D3D12CommandProcessor;
class DeferredCommandList {
public:
static constexpr size_t MAX_SIZEOF_COMMANDLIST = 65536 * 128; //around 8 mb
static constexpr size_t MAX_SIZEOF_COMMANDLIST = 65536 * 128; // around 8 mb
/*
chrispy: upped from 1_MiB to 4_MiB, m:durandal hits frequent resizes in large open maps
chrispy: upped from 1_MiB to 4_MiB, m:durandal hits frequent resizes in
large open maps
*/
DeferredCommandList(const D3D12CommandProcessor& command_processor,
size_t initial_size_bytes = MAX_SIZEOF_COMMANDLIST);
@@ -566,7 +567,7 @@ class DeferredCommandList {
const D3D12CommandProcessor& command_processor_;
// uintmax_t to ensure uint64_t and pointer alignment of all structures.
//std::vector<uintmax_t> command_stream_;
// std::vector<uintmax_t> command_stream_;
FixedVMemVector<MAX_SIZEOF_COMMANDLIST> command_stream_;
};