[LINT] Linted files + Added lint job to CI
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committed by
Radosław Gliński
parent
e8afad8f8a
commit
b9061e6292
@@ -13,7 +13,7 @@
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// Almost all of these values are taken directly from:
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// https://github.com/freedreno/amd-gpu/blob/master/include/reg/yamato/22/yamato_offset.h
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//#define XE_GPU_REGISTER(index, type, name)
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// #define XE_GPU_REGISTER(index, type, name)
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XE_GPU_REGISTER(0x0048, kDword, BIF_PERFCOUNTER0_SELECT)
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XE_GPU_REGISTER(0x0049, kDword, BIF_PERFCOUNTER0_HI)
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@@ -36,35 +36,36 @@ XE_GPU_REGISTER(0x0398, kDword, RBBM_PERFCOUNTER0_HI)
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XE_GPU_REGISTER(0x0399, kDword, RBBM_PERFCOUNTER1_LOW)
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XE_GPU_REGISTER(0x039A, kDword, RBBM_PERFCOUNTER1_HI)
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//XAM reads this directly and stores it to a struct, have not tracked where it goes from there
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//PM4 command PM4_MEM_WRITE_CNTR is supposed to write this to memory
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//XE_GPU_REGISTER(0x44b, kDword,CP_PROG_COUNTER )
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// XAM reads this directly and stores it to a struct, have not tracked where it
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// goes from there PM4 command PM4_MEM_WRITE_CNTR is supposed to write this to
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// memory XE_GPU_REGISTER(0x44b, kDword,CP_PROG_COUNTER )
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XE_GPU_REGISTER(0x045E, kDword, CALLBACK_ACK)
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XE_GPU_REGISTER(0x0578, kDword, SCRATCH_REG0) // interrupt sync
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XE_GPU_REGISTER(0x0579, kDword, SCRATCH_REG1) // present interval
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XE_GPU_REGISTER(0x057A, kDword, SCRATCH_REG2)
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XE_GPU_REGISTER(0x057B, kDword, SCRATCH_REG3)
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XE_GPU_REGISTER(0x057C, kDword, SCRATCH_REG4) //originally this was named CALLBACK_ADDRESS, but that didnt make sense
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XE_GPU_REGISTER(0x057C, kDword,
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SCRATCH_REG4) // originally this was named CALLBACK_ADDRESS,
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// but that didnt make sense
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XE_GPU_REGISTER(0x057D, kDword, SCRATCH_REG5)
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XE_GPU_REGISTER(0x057E, kDword, SCRATCH_REG6)
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XE_GPU_REGISTER(0x057F, kDword, SCRATCH_REG7)
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XE_GPU_REGISTER(0x05C8, kDword, WAIT_UNTIL)
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//src is flash_xam.xex, i've seen it used by the kernel and aurora
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//seems to have a negative value while the gpu is busy
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//XE_GPU_REGISTER(0x05D0, kDword, RBBM_STATUS)
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// src is flash_xam.xex, i've seen it used by the kernel and aurora
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// seems to have a negative value while the gpu is busy
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// XE_GPU_REGISTER(0x05D0, kDword, RBBM_STATUS)
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// update count = 6 bit field, bits 8- 14
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// there are several other fields here, they have an unknown purpose
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// XE_GPU_REGISTER(0x704, kDword, CP_RB_CNTL)
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//update count = 6 bit field, bits 8- 14
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//there are several other fields here, they have an unknown purpose
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//XE_GPU_REGISTER(0x704, kDword, CP_RB_CNTL)
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//address must be 4 byte aligned
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//low 2 bits encode two different fields?
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//xboxkrnl just does addr |2 when assigning
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//XE_GPU_REGISTER(0x70C, kDword, CP_RB_RPTR_ADDR)
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// address must be 4 byte aligned
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// low 2 bits encode two different fields?
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// xboxkrnl just does addr |2 when assigning
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// XE_GPU_REGISTER(0x70C, kDword, CP_RB_RPTR_ADDR)
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XE_GPU_REGISTER(0x0815, kDword, MC0_PERFCOUNTER0_SELECT)
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XE_GPU_REGISTER(0x0816, kDword, MC0_PERFCOUNTER0_HI)
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XE_GPU_REGISTER(0x0817, kDword, MC0_PERFCOUNTER0_LOW)
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@@ -72,13 +73,13 @@ XE_GPU_REGISTER(0x0855, kDword, MC1_PERFCOUNTER0_SELECT)
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XE_GPU_REGISTER(0x0856, kDword, MC1_PERFCOUNTER0_HI)
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XE_GPU_REGISTER(0x0857, kDword, MC1_PERFCOUNTER0_LOW)
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//base GPU virtual address of the xps region. Most guests write 0xC0100000 here
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// base GPU virtual address of the xps region. Most guests write 0xC0100000 here
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XE_GPU_REGISTER(0x0A02, kDword, XPS_BASE)
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//will usually be set higher, but is effectively 0x700000 bytes long
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// will usually be set higher, but is effectively 0x700000 bytes long
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XE_GPU_REGISTER(0x0A03, kDword, XPS_SIZE)
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//usually 0xC0000000
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// usually 0xC0000000
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XE_GPU_REGISTER(0x0A04, kDword, WRITEBACK_BASE)
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//usually 0x0100000
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// usually 0x0100000
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XE_GPU_REGISTER(0x0A05, kDword, WRITEBACK_SIZE)
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XE_GPU_REGISTER(0x0A18, kDword, MH_PERFCOUNTER0_SELECT)
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@@ -279,8 +280,8 @@ XE_GPU_REGISTER(0x0F0C, kDword, BC_PERFCOUNTER2_LOW)
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XE_GPU_REGISTER(0x0F0D, kDword, BC_PERFCOUNTER2_HI)
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XE_GPU_REGISTER(0x0F0E, kDword, BC_PERFCOUNTER3_LOW)
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XE_GPU_REGISTER(0x0F0F, kDword, BC_PERFCOUNTER3_HI)
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//src is flash_xam.xex
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//XE_GPU_REGISTER(0x0F12, RB_SIDEBAND_DATA,
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// src is flash_xam.xex
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// XE_GPU_REGISTER(0x0F12, RB_SIDEBAND_DATA,
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XE_GPU_REGISTER(0x1004, kDword, HZ_PERFCOUNTER0_SELECT)
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XE_GPU_REGISTER(0x1005, kDword, HZ_PERFCOUNTER0_HI)
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