[CPU] Data cache control instructions

This commit is contained in:
Triang3l
2019-08-18 16:14:51 +03:00
parent c19dc9c7d6
commit bc4b68db45
6 changed files with 105 additions and 32 deletions

View File

@@ -1277,12 +1277,12 @@ void HIRBuilder::Memset(Value* address, Value* value, Value* length) {
i->set_src3(length);
}
void HIRBuilder::Prefetch(Value* address, size_t length,
uint32_t prefetch_flags) {
void HIRBuilder::CacheControl(Value* address, size_t cache_line_size,
CacheControlType type) {
ASSERT_ADDRESS_TYPE(address);
Instr* i = AppendInstr(OPCODE_PREFETCH_info, prefetch_flags);
Instr* i = AppendInstr(OPCODE_CACHE_CONTROL_info, uint32_t(type));
i->set_src1(address);
i->src2.offset = length;
i->src2.offset = cache_line_size;
i->src3.value = NULL;
}

View File

@@ -157,7 +157,8 @@ class HIRBuilder {
Value* Load(Value* address, TypeName type, uint32_t load_flags = 0);
void Store(Value* address, Value* value, uint32_t store_flags = 0);
void Memset(Value* address, Value* value, Value* length);
void Prefetch(Value* address, size_t length, uint32_t prefetch_flags = 0);
void CacheControl(Value* address, size_t cache_line_size,
CacheControlType type);
void MemoryBarrier();
void SetRoundingMode(Value* value);

View File

@@ -39,9 +39,11 @@ enum LoadStoreFlags {
LOAD_STORE_BYTE_SWAP = 1 << 0,
};
enum PrefetchFlags {
PREFETCH_LOAD = (1 << 1),
PREFETCH_STORE = (1 << 2),
enum CacheControlType {
CACHE_CONTOROL_TYPE_DATA_TOUCH,
CACHE_CONTOROL_TYPE_DATA_TOUCH_FOR_STORE,
CACHE_CONTOROL_TYPE_DATA_STORE,
CACHE_CONTOROL_TYPE_DATA_STORE_AND_FLUSH,
};
enum ArithmeticFlags {
@@ -158,7 +160,7 @@ enum Opcode {
OPCODE_LOAD,
OPCODE_STORE,
OPCODE_MEMSET,
OPCODE_PREFETCH,
OPCODE_CACHE_CONTROL,
OPCODE_MEMORY_BARRIER,
OPCODE_MAX,
OPCODE_VECTOR_MAX,

View File

@@ -262,8 +262,8 @@ DEFINE_OPCODE(
OPCODE_FLAG_MEMORY)
DEFINE_OPCODE(
OPCODE_PREFETCH,
"prefetch",
OPCODE_CACHE_CONTROL,
"cache_control",
OPCODE_SIG_X_V_O,
OPCODE_FLAG_MEMORY)