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[CPU] Data cache control instructions

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This commit is contained in:
Triang3l
2019-08-18 16:14:51 +03:00
parent c19dc9c7d6
commit bc4b68db45
6 changed files with 105 additions and 32 deletions
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8
src/xenia/cpu/hir/hir_builder.cc
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@@ -1277,12 +1277,12 @@ void HIRBuilder::Memset(Value* address, Value* value, Value* length) {
i->set_src3(length);
}
void HIRBuilder::Prefetch(Value* address, size_t length,
uint32_t prefetch_flags) {
void HIRBuilder::CacheControl(Value* address, size_t cache_line_size,
CacheControlType type) {
ASSERT_ADDRESS_TYPE(address);
Instr* i = AppendInstr(OPCODE_PREFETCH_info, prefetch_flags);
Instr* i = AppendInstr(OPCODE_CACHE_CONTROL_info, uint32_t(type));
i->set_src1(address);
i->src2.offset = length;
i->src2.offset = cache_line_size;
i->src3.value = NULL;
}