[CPU] Data cache control instructions

2019-08-18 16:14:51 +03:00
parent c19dc9c7d6
commit bc4b68db45
6 changed files with 105 additions and 32 deletions
--- a/src/xenia/cpu/hir/hir_builder.h
+++ b/src/xenia/cpu/hir/hir_builder.h
@@ -157,7 +157,8 @@ class HIRBuilder {
  Value* Load(Value* address, TypeName type, uint32_t load_flags = 0);
  void Store(Value* address, Value* value, uint32_t store_flags = 0);
  void Memset(Value* address, Value* value, Value* length);
-  void Prefetch(Value* address, size_t length, uint32_t prefetch_flags = 0);
+  void CacheControl(Value* address, size_t cache_line_size,
+                    CacheControlType type);
  void MemoryBarrier();

  void SetRoundingMode(Value* value);