[CPU] Data cache control instructions

src/xenia/cpu/hir/opcodes.h

@@ -39,9 +39,11 @@ enum LoadStoreFlags {
   LOAD_STORE_BYTE_SWAP = 1 << 0,
 };
 
-enum PrefetchFlags {
-  PREFETCH_LOAD = (1 << 1),
-  PREFETCH_STORE = (1 << 2),
+enum CacheControlType {
+  CACHE_CONTOROL_TYPE_DATA_TOUCH,
+  CACHE_CONTOROL_TYPE_DATA_TOUCH_FOR_STORE,
+  CACHE_CONTOROL_TYPE_DATA_STORE,
+  CACHE_CONTOROL_TYPE_DATA_STORE_AND_FLUSH,
 };
 
 enum ArithmeticFlags {
@@ -158,7 +160,7 @@ enum Opcode {
   OPCODE_LOAD,
   OPCODE_STORE,
   OPCODE_MEMSET,
-  OPCODE_PREFETCH,
+  OPCODE_CACHE_CONTROL,
   OPCODE_MEMORY_BARRIER,
   OPCODE_MAX,
   OPCODE_VECTOR_MAX,