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[GPU] Common resolve code based on compute shaders, swap MSAA samples 1 and 2, change ROV write rounding, random refactoring

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Triang3l
2020-08-09 21:33:10 +03:00
parent 72e41e2bf8
commit bd5f77bc3b
378 changed files with 72288 additions and 37207 deletions
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8
src/xenia/gpu/registers.h
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@@ -394,7 +394,7 @@ union RB_MODECONTROL {
union RB_SURFACE_INFO {
struct {
uint32_t surface_pitch : 14; // +0
uint32_t surface_pitch : 14; // +0 in pixels.
uint32_t : 2; // +14
xenos::MsaaSamples msaa_samples : 2; // +16
uint32_t hiz_pitch : 14; // +18
@@ -454,7 +454,7 @@ union RB_COLORCONTROL {
union RB_COLOR_INFO {
struct {
uint32_t color_base : 12; // +0
uint32_t color_base : 12; // +0 in tiles.
uint32_t : 4; // +12
xenos::ColorRenderTargetFormat color_format : 4; // +16
int32_t color_exp_bias : 6; // +20
@@ -540,7 +540,7 @@ union RB_STENCILREFMASK {
union RB_DEPTH_INFO {
struct {
uint32_t depth_base : 12; // +0
uint32_t depth_base : 12; // +0 in tiles.
uint32_t : 4; // +12
xenos::DepthRenderTargetFormat depth_format : 1; // +16
};
@@ -548,6 +548,8 @@ union RB_DEPTH_INFO {
static constexpr Register register_index = XE_GPU_REG_RB_DEPTH_INFO;
};
// Copy registers are very different than on Adreno.
union RB_COPY_CONTROL {
struct {
uint32_t copy_src_select : 3; // +0 Depth is 4.