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[a64] Implement OPCODE_CACHE_CONTROL store

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This commit is contained in:
Wunkolo
2026-03-24 13:38:11 -07:00
committed by Heel
parent 5b9c13b23f
commit bf83c4e9f5
1 changed files with 11 additions and 4 deletions
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15
src/xenia/cpu/backend/a64/a64_seq_memory.cc
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@@ -76,7 +76,7 @@ struct CACHE_CONTROL
: Sequence<CACHE_CONTROL,
I<OPCODE_CACHE_CONTROL, VoidOp, I64Op, OffsetOp>> {
static void Emit(A64Emitter& e, const EmitArgType& i) {
bool is_prefetch = false, is_prefetchw = false;
bool is_clflush = false, is_prefetch = false, is_prefetchw = false;
switch (CacheControlType(i.instr->flags)) {
case CacheControlType::CACHE_CONTROL_TYPE_DATA_TOUCH:
is_prefetch = true;
@@ -86,15 +86,18 @@ struct CACHE_CONTROL
break;
case CacheControlType::CACHE_CONTROL_TYPE_DATA_STORE:
case CacheControlType::CACHE_CONTROL_TYPE_DATA_STORE_AND_FLUSH:
// ARM64 dc instructions aren't available in xbyak_aarch64.
// These are mostly hints anyway; skip.
return;
is_clflush = true;
break;
default:
return;
}
auto addr = ComputeMemoryAddress(e, i.src1);
e.add(e.x0, e.GetMembaseReg(), addr);
size_t cache_line_size = i.src2.value;
if (is_clflush) {
// dc civac, x0
e.sys(0b011, 0b0111, 0b1110, 0b001, e.x0);
}
if (is_prefetch) {
e.prfm(Xbyak_aarch64::PLDL1KEEP, ptr(e.x0));
} else if (is_prefetchw) {
@@ -102,6 +105,10 @@ struct CACHE_CONTROL
}
if (cache_line_size >= 128) {
e.eor(e.x0, e.x0, 64);
if (is_clflush) {
// dc civac, x0
e.sys(0b011, 0b0111, 0b1110, 0b001, e.x0);
}
if (is_prefetch) {
e.prfm(Xbyak_aarch64::PLDL1KEEP, ptr(e.x0));
} else if (is_prefetchw) {