Minor decoder optimizations, kernel fixes, cpu backend fixes

src/xenia/gpu/d3d12/d3d12_command_processor.cc

@@ -2042,10 +2042,6 @@ D3D12CommandProcessor::WriteRegisterRangeFromRing_WithKnownBound(
   RingBuffer::ReadRange range =
       ring->BeginRead(num_registers * sizeof(uint32_t));
 
-  constexpr auto bounds_has_reg =
-      bounds_may_have_reg<register_lower_bound, register_upper_bound>;
-  constexpr auto bounds_has_bounds =
-      bounds_may_have_bounds<register_lower_bound, register_upper_bound>;
 
   XE_LIKELY_IF(!range.second) {
     WriteRegisterRangeFromMem_WithKnownBound<register_lower_bound,
@@ -5152,6 +5148,7 @@ void D3D12CommandProcessor::WriteGammaRampSRV(
 #define COMMAND_PROCESSOR D3D12CommandProcessor
 
 #include "../pm4_command_processor_implement.h"
+#undef COMMAND_PROCESSOR
 }  // namespace d3d12
 }  // namespace gpu
 }  // namespace xe

src/xenia/gpu/d3d12/d3d12_command_processor.h

@@ -1,5 +1,3 @@
-/**
-/**
 /**
  ******************************************************************************
  * Xenia : Xbox 360 Emulator Research Project                                 *
@@ -50,8 +48,9 @@ struct MemExportRange {
 };
 class D3D12CommandProcessor final : public CommandProcessor {
  protected:
+#define OVERRIDING_BASE_CMDPROCESSOR
 #include "../pm4_command_processor_declare.h"
-
+#undef OVERRIDING_BASE_CMDPROCESSOR
  public:
   explicit D3D12CommandProcessor(D3D12GraphicsSystem* graphics_system,
                                  kernel::KernelState* kernel_state);

src/xenia/gpu/d3d12/d3d12_nvapi.hpp

@@ -108,15 +108,4 @@ inline nvapi_state_t::~nvapi_state_t() {
     call_deinit_interface();
   }
 }
-inline void init_nvapi() {
-  /// HMODULE moddy = LoadLibraryA("nvapi64.dll");
-
-  // FARPROC quif = GetProcAddress(moddy, "nvapi_QueryInterface");
-
-  nvapi_state_t nvapi{};
-
-  auto queryvisible = nvapi.query_interface<void>(0x26322BC3);
-  return;
-}
-
 }  // namespace lightweight_nvapi

src/xenia/gpu/d3d12/d3d12_texture_cache.h

@@ -87,7 +87,7 @@ class D3D12TextureCache final : public TextureCache {
 
   ~D3D12TextureCache();
 
-  void ClearCache();
+  void ClearCache() override;
 
   void BeginSubmission(uint64_t new_submission_index) override;
   void BeginFrame() override;

src/xenia/gpu/pm4_command_processor_declare.h

@@ -1,8 +1,15 @@
 
 
-void ExecuteIndirectBuffer(uint32_t ptr, uint32_t count) XE_RESTRICT;
-virtual uint32_t ExecutePrimaryBuffer(uint32_t start_index, uint32_t end_index) XE_RESTRICT;
-virtual bool ExecutePacket();
+#if defined(OVERRIDING_BASE_CMDPROCESSOR)
+#define	PM4_OVERRIDE		override
+#else
+#define PM4_OVERRIDE
+#endif
+void ExecuteIndirectBuffer(uint32_t ptr,
+                           uint32_t count) XE_RESTRICT;
+virtual uint32_t ExecutePrimaryBuffer(uint32_t start_index, uint32_t end_index)
+    XE_RESTRICT PM4_OVERRIDE;
+virtual bool ExecutePacket() PM4_OVERRIDE;
 
 public:
 void ExecutePacket(uint32_t ptr, uint32_t count);
@@ -111,4 +118,6 @@ XE_COLD
 bool ExecutePacketType3_CountOverflow(uint32_t count);
 XE_NOINLINE
 XE_COLD
-bool ExecutePacketType0_CountOverflow(uint32_t count);
+bool ExecutePacketType0_CountOverflow(uint32_t count);
+
+#undef PM4_OVERRIDE

src/xenia/gpu/pm4_command_processor_implement.h

@@ -4,32 +4,38 @@ void COMMAND_PROCESSOR::ExecuteIndirectBuffer(uint32_t ptr,
                                               uint32_t count) XE_RESTRICT {
   SCOPE_profile_cpu_f("gpu");
 
+
   trace_writer_.WriteIndirectBufferStart(ptr, count * sizeof(uint32_t));
+  if (count != 0) {
+    RingBuffer old_reader = reader_;
 
-  RingBuffer old_reader = reader_;
+    // Execute commands!
+    new (&reader_)
+        RingBuffer(memory_->TranslatePhysical(ptr), count * sizeof(uint32_t));
+    reader_.set_write_offset(count * sizeof(uint32_t));
+    // prefetch the wraparound range
+    // it likely is already in L3 cache, but in a zen system it may be another
+    // chiplets l3
+    reader_.BeginPrefetchedRead<swcache::PrefetchTag::Level2>(
+        COMMAND_PROCESSOR::GetCurrentRingReadCount());
+    do {
+      if (COMMAND_PROCESSOR::ExecutePacket()) {
+        continue;
+      } else {
+        // Return up a level if we encounter a bad packet.
+        XELOGE("**** INDIRECT RINGBUFFER: Failed to execute packet.");
+        assert_always();
+        // break;
+      }
+    } while (reader_.read_count());
 
-  // Execute commands!
-  new (&reader_)
-      RingBuffer(memory_->TranslatePhysical(ptr), count * sizeof(uint32_t));
-  reader_.set_write_offset(count * sizeof(uint32_t));
-  // prefetch the wraparound range
-  // it likely is already in L3 cache, but in a zen system it may be another
-  // chiplets l3
-  reader_.BeginPrefetchedRead<swcache::PrefetchTag::Level2>(
-      COMMAND_PROCESSOR::GetCurrentRingReadCount());
-  do {
-    if (COMMAND_PROCESSOR::ExecutePacket()) {
-      continue;
-    } else {
-      // Return up a level if we encounter a bad packet.
-      XELOGE("**** INDIRECT RINGBUFFER: Failed to execute packet.");
-      assert_always();
-      // break;
-    }
-  } while (reader_.read_count());
+    trace_writer_.WriteIndirectBufferEnd();
+    reader_ = old_reader;
+  } else {
+	  //rare, but i've seen it happen! (and then a division by 0 occurs)
+    return;
+  }
 
-  trace_writer_.WriteIndirectBufferEnd();
-  reader_ = old_reader;
 }
 
 bool COMMAND_PROCESSOR::ExecutePacket() {

src/xenia/gpu/render_target_cache.h

@@ -229,9 +229,10 @@ class RenderTargetCache {
                     TraceWriter* trace_writer, uint32_t draw_resolution_scale_x,
                     uint32_t draw_resolution_scale_y)
       : register_file_(register_file),
-        draw_extent_estimator_(register_file, memory, trace_writer),
         draw_resolution_scale_x_(draw_resolution_scale_x),
-        draw_resolution_scale_y_(draw_resolution_scale_y) {
+        draw_resolution_scale_y_(draw_resolution_scale_y),
+        draw_extent_estimator_(register_file, memory, trace_writer)
+  {
     assert_not_zero(draw_resolution_scale_x);
     assert_not_zero(draw_resolution_scale_y);
   }

src/xenia/gpu/trace_viewer.cc

@@ -941,7 +941,6 @@ void TraceViewer::DrawVertexFetcher(Shader* shader,
           ImGui::NextColumn();
           break;
         case xenos::VertexFormat::k_2_10_10_10: {
-          auto e0 = LOADEL(uint32_t, 0);
           ImGui::Text("??");
           ImGui::NextColumn();
           ImGui::Text("??");
@@ -1066,8 +1065,6 @@ void ProgressBar(float frac, float width, float height = 0,
   }
   frac = xe::saturate_unsigned(frac);
 
-  const auto fontAtlas = ImGui::GetIO().Fonts;
-
   auto pos = ImGui::GetCursorScreenPos();
   auto col = ImGui::ColorConvertFloat4ToU32(color);
   auto border_col = ImGui::ColorConvertFloat4ToU32(border_color);
@@ -1137,7 +1134,6 @@ void TraceViewer::DrawStateUI() {
   std::memset(&draw_info, 0, sizeof(draw_info));
   switch (opcode) {
     case PM4_DRAW_INDX: {
-      uint32_t dword0 = xe::load_and_swap<uint32_t>(packet_head + 4);
       uint32_t dword1 = xe::load_and_swap<uint32_t>(packet_head + 8);
       draw_info.index_count = dword1 >> 16;
       draw_info.prim_type = static_cast<xenos::PrimitiveType>(dword1 & 0x3F);
@@ -1187,7 +1183,6 @@ void TraceViewer::DrawStateUI() {
   auto enable_mode =
       static_cast<ModeControl>(regs[XE_GPU_REG_RB_MODECONTROL].u32 & 0x7);
 
-  const char* mode_name = "Unknown";
   switch (enable_mode) {
     case ModeControl::kIgnore:
       ImGui::Text("Ignored Command %d", player_->current_command_index());

src/xenia/gpu/vulkan/vulkan_command_processor.h

@@ -48,8 +48,9 @@ namespace vulkan {
 
 class VulkanCommandProcessor final : public CommandProcessor {
  protected:
+#define OVERRIDING_BASE_CMDPROCESSOR
 #include "../pm4_command_processor_declare.h"
-
+#undef OVERRIDING_BASE_CMDPROCESSOR
  public:
   // Single-descriptor layouts for use within a single frame.
   enum class SingleTransientDescriptorLayout {