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nasty commit with a bunch of test code left in, will clean up and pr

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Remove the logger_ != nullptr check from shouldlog, it will nearly always be true except on initialization and gets checked later anyway, this shrinks the size of the generated code for some
Select specialized vastcpy for current cpu, for now only have paths for MOVDIR64B and generic avx1
Add XE_UNLIKELY/LIKELY if, they map better to the c++ unlikely/likely attributes which we will need to use soon
Finished reimplementing STVL/STVR/LVL/LVR as their own opcodes. we now generate far less code for these instructions. this also means optimization passes can be written to simplify/remove/replace these instructions in some cases. Found that a good deal of the X86 we were emitting for these instructions was dead code or redundant.
the reduction in generated HIR/x86 should help a lot with compilation times and make function precompilation more feasible as a default

Don't static assert in default prefetch impl, in c++20 the assertion will be triggered even without an instantiation
Reorder some if/else to prod msvc into ordering the branches optimally. it somewhat worked...
Added some notes about which opcodes should be removed/refactored
Dispatch in WriteRegister via vector compares for the bounds. still not very optimal, we ought to be checking whether any register in a range may be special
A lot of work on trying to optimize writeregister, moved wraparound path into a noinline function based on profiling info
Hoist the IsUcodeAnalyzed check out of AnalyzeShader, instead check it before each call. Profiler recorded many hits in the stack frame setup of the function, but none in the actual body of it, so the check is often true but the stack frame setup is run unconditionally
Pre-check whether we're about to write a single register from a ring
Replace more jump tables from draw_util/texture_info with popcnt based sparse indexing/bit tables/shuffle lookups
Place the GPU register file on its own VAD/virtual allocation, it is no longer a member of graphics system
This commit is contained in:
chss95cs@gmail.com
2022-09-04 11:04:41 -07:00
parent 78c9a48bc2
commit c6010bd4b1
20 changed files with 975 additions and 178 deletions
Download Patch File Download Diff File Expand all files Collapse all files

152
src/xenia/gpu/command_processor.cc
View File

@@ -29,20 +29,6 @@
#include "xenia/kernel/kernel_state.h"
#include "xenia/kernel/user_module.h"
#if defined(NDEBUG)
static constexpr bool should_log_unknown_reg_writes() { return false; }
#else
DEFINE_bool(log_unknown_register_writes, false,
"Log writes to unknown registers from "
"CommandProcessor::WriteRegister. Has significant performance hit.",
"GPU");
static bool should_log_unknown_reg_writes() {
return cvars::log_unknown_register_writes;
}
#endif
namespace xe {
namespace gpu {
@@ -475,44 +461,34 @@ void CommandProcessor::HandleSpecialRegisterWrite(uint32_t index,
}
}
void CommandProcessor::WriteRegister(uint32_t index, uint32_t value) {
if (should_log_unknown_reg_writes()) {
// chrispy: rearrange check order, place set after checks
if (XE_UNLIKELY(!register_file_->IsValidRegister(index))) {
XELOGW("GPU: Write to unknown register ({:04X} = {:08X})", index, value);
check_reg_out_of_bounds:
if (XE_UNLIKELY(index >= RegisterFile::kRegisterCount)) {
XELOGW("CommandProcessor::WriteRegister index out of bounds: {}",
index);
return;
}
// chrispy: rearrange check order, place set after checks
if (XE_LIKELY(index < RegisterFile::kRegisterCount)) {
register_file_->values[index].u32 = value;
// quick pre-test
// todo: figure out just how unlikely this is. if very (it ought to be,
// theres a ton of registers other than these) make this predicate
// branchless and mark with unlikely, then make HandleSpecialRegisterWrite
// noinline yep, its very unlikely. these ORS here are meant to be bitwise
// ors, so that we do not do branching evaluation of the conditions (we will
// almost always take all of the branches)
unsigned expr = (index - XE_GPU_REG_SCRATCH_REG0 < 8) |
(index == XE_GPU_REG_COHER_STATUS_HOST) |
((index - XE_GPU_REG_DC_LUT_RW_INDEX) <=
(XE_GPU_REG_DC_LUT_30_COLOR - XE_GPU_REG_DC_LUT_RW_INDEX));
// chrispy: reordered for msvc branch probability (assumes if is taken and
// else is not)
if (XE_LIKELY(expr == 0)) {
XE_MSVC_REORDER_BARRIER();
} else {
HandleSpecialRegisterWrite(index, value);
}
} else {
goto check_reg_out_of_bounds;
}
register_file_->values[index].u32 = value;
// regs with extra logic on write: XE_GPU_REG_COHER_STATUS_HOST
// XE_GPU_REG_DC_LUT_RW_INDEX
// XE_GPU_REG_DC_LUT_SEQ_COLOR XE_GPU_REG_DC_LUT_PWL_DATA
// XE_GPU_REG_DC_LUT_30_COLOR
// quick pre-test
// todo: figure out just how unlikely this is. if very (it ought to be, theres
// a ton of registers other than these) make this predicate branchless and
// mark with unlikely, then make HandleSpecialRegisterWrite noinline yep, its
// very unlikely. these ORS here are meant to be bitwise ors, so that we do
// not do branching evaluation of the conditions (we will almost always take
// all of the branches)
unsigned expr = (index - XE_GPU_REG_SCRATCH_REG0 < 8) |
(index == XE_GPU_REG_COHER_STATUS_HOST) |
((index - XE_GPU_REG_DC_LUT_RW_INDEX) <=
(XE_GPU_REG_DC_LUT_30_COLOR - XE_GPU_REG_DC_LUT_RW_INDEX));
// chrispy: reordered for msvc branch probability (assumes if is taken and
// else is not)
if (XE_LIKELY(expr == 0)) {
} else {
HandleSpecialRegisterWrite(index, value);
XELOGW("CommandProcessor::WriteRegister index out of bounds: {}", index);
return;
}
}
void CommandProcessor::WriteRegistersFromMem(uint32_t start_index,
@@ -587,7 +563,7 @@ void CommandProcessor::ReturnFromWait() {}
uint32_t CommandProcessor::ExecutePrimaryBuffer(uint32_t read_index,
uint32_t write_index) {
SCOPE_profile_cpu_f("gpu");
#if XE_ENABLE_TRACE_WRITER_INSTRUMENTATION == 1
// If we have a pending trace stream open it now. That way we ensure we get
// all commands.
if (!trace_writer_.is_open() && trace_state_ == TraceState::kStreaming) {
@@ -599,7 +575,7 @@ uint32_t CommandProcessor::ExecutePrimaryBuffer(uint32_t read_index,
trace_writer_.Open(path, title_id);
InitializeTrace();
}
#endif
// Adjust pointer base.
uint32_t start_ptr = primary_buffer_ptr_ + read_index * sizeof(uint32_t);
start_ptr = (primary_buffer_ptr_ & ~0x1FFFFFFF) | (start_ptr & 0x1FFFFFFF);
@@ -676,22 +652,24 @@ bool CommandProcessor::ExecutePacket(RingBuffer* reader) {
return true;
}
if (XE_UNLIKELY(packet == 0xCDCDCDCD)) {
if (XE_LIKELY(packet != 0xCDCDCDCD)) {
actually_execute_packet:
switch (packet_type) {
case 0x00:
return ExecutePacketType0(reader, packet);
case 0x01:
return ExecutePacketType1(reader, packet);
case 0x02:
return ExecutePacketType2(reader, packet);
case 0x03:
return ExecutePacketType3(reader, packet);
default:
assert_unhandled_case(packet_type);
return false;
}
} else {
XELOGW("GPU packet is CDCDCDCD - probably read uninitialized memory!");
}
switch (packet_type) {
case 0x00:
return ExecutePacketType0(reader, packet);
case 0x01:
return ExecutePacketType1(reader, packet);
case 0x02:
return ExecutePacketType2(reader, packet);
case 0x03:
return ExecutePacketType3(reader, packet);
default:
assert_unhandled_case(packet_type);
return false;
goto actually_execute_packet;
}
}
@@ -712,10 +690,15 @@ bool CommandProcessor::ExecutePacketType0(RingBuffer* reader, uint32_t packet) {
uint32_t base_index = (packet & 0x7FFF);
uint32_t write_one_reg = (packet >> 15) & 0x1;
if (write_one_reg) {
WriteOneRegisterFromRing(reader, base_index, count);
if (!write_one_reg) {
if (count == 1) {
WriteRegister(base_index, reader->ReadAndSwap<uint32_t>());
} else {
WriteRegisterRangeFromRing(reader, base_index, count);
}
} else {
WriteRegisterRangeFromRing(reader, base_index, count);
WriteOneRegisterFromRing(reader, base_index, count);
}
trace_writer_.WritePacketEnd();
@@ -750,7 +733,7 @@ bool CommandProcessor::ExecutePacketType3(RingBuffer* reader, uint32_t packet) {
uint32_t count = ((packet >> 16) & 0x3FFF) + 1;
auto data_start_offset = reader->read_offset();
if (reader->read_count() < count * sizeof(uint32_t)) {
XE_UNLIKELY_IF(reader->read_count() < count * sizeof(uint32_t)) {
XELOGE(
"ExecutePacketType3 overflow (read count {:08X}, packet count {:08X})",
reader->read_count(), count * sizeof(uint32_t));
@@ -914,6 +897,8 @@ bool CommandProcessor::ExecutePacketType3(RingBuffer* reader, uint32_t packet) {
}
trace_writer_.WritePacketEnd();
#if XE_ENABLE_TRACE_WRITER_INSTRUMENTATION == 1
if (opcode == PM4_XE_SWAP) {
// End the trace writer frame.
if (trace_writer_.is_open()) {
@@ -932,6 +917,7 @@ bool CommandProcessor::ExecutePacketType3(RingBuffer* reader, uint32_t packet) {
InitializeTrace();
}
}
#endif
assert_true(reader->read_offset() ==
(data_start_offset + (count * sizeof(uint32_t))) %
@@ -1512,9 +1498,13 @@ bool CommandProcessor::ExecutePacketType3_SET_CONSTANT(RingBuffer* reader,
reader->AdvanceRead((count - 1) * sizeof(uint32_t));
return true;
}
uint32_t countm1 = count - 1;
WriteRegisterRangeFromRing(reader, index, count - 1);
if (countm1 != 1) {
WriteRegisterRangeFromRing(reader, index, countm1);
} else {
WriteRegister(index, reader->ReadAndSwap<uint32_t>());
}
return true;
}
@@ -1523,9 +1513,13 @@ bool CommandProcessor::ExecutePacketType3_SET_CONSTANT2(RingBuffer* reader,
uint32_t count) {
uint32_t offset_type = reader->ReadAndSwap<uint32_t>();
uint32_t index = offset_type & 0xFFFF;
uint32_t countm1 = count - 1;
WriteRegisterRangeFromRing(reader, index, count - 1);
if (countm1 != 1) {
WriteRegisterRangeFromRing(reader, index, countm1);
} else {
WriteRegister(index, reader->ReadAndSwap<uint32_t>());
}
return true;
}
@@ -1573,8 +1567,12 @@ bool CommandProcessor::ExecutePacketType3_SET_SHADER_CONSTANTS(
RingBuffer* reader, uint32_t packet, uint32_t count) {
uint32_t offset_type = reader->ReadAndSwap<uint32_t>();
uint32_t index = offset_type & 0xFFFF;
WriteRegisterRangeFromRing(reader, index, count - 1);
uint32_t countm1 = count - 1;
if (countm1 != 1) {
WriteRegisterRangeFromRing(reader, index, countm1);
} else {
WriteRegister(index, reader->ReadAndSwap<uint32_t>());
}
return true;
}

137
src/xenia/gpu/d3d12/d3d12_command_processor.cc
View File

@@ -1678,11 +1678,79 @@ void D3D12CommandProcessor::ShutdownContext() {
}
// todo: bit-pack the bools and use bitarith to reduce branches
void D3D12CommandProcessor::WriteRegister(uint32_t index, uint32_t value) {
CommandProcessor::WriteRegister(index, value);
#if XE_ARCH_AMD64 == 1
// CommandProcessor::WriteRegister(index, value);
bool cbuf_binding_float_pixel_utd = cbuffer_binding_float_pixel_.up_to_date;
bool cbuf_binding_float_vertex_utd = cbuffer_binding_float_vertex_.up_to_date;
bool cbuf_binding_bool_loop_utd = cbuffer_binding_bool_loop_.up_to_date;
__m128i to_rangecheck = _mm_set1_epi16(static_cast<short>(index));
__m128i lower_bounds = _mm_setr_epi16(
XE_GPU_REG_SHADER_CONSTANT_FETCH_00_0 - 1,
XE_GPU_REG_SHADER_CONSTANT_000_X - 1,
XE_GPU_REG_SHADER_CONSTANT_BOOL_000_031 - 1, XE_GPU_REG_SCRATCH_REG0 - 1,
XE_GPU_REG_COHER_STATUS_HOST - 1, XE_GPU_REG_DC_LUT_RW_INDEX - 1, 0, 0);
__m128i upper_bounds = _mm_setr_epi16(
XE_GPU_REG_SHADER_CONSTANT_FETCH_31_5 + 1,
XE_GPU_REG_SHADER_CONSTANT_511_W + 1,
XE_GPU_REG_SHADER_CONSTANT_LOOP_31 + 1, XE_GPU_REG_SCRATCH_REG7 + 1,
XE_GPU_REG_COHER_STATUS_HOST + 1, XE_GPU_REG_DC_LUT_30_COLOR + 1, 0, 0);
// quick pre-test
// todo: figure out just how unlikely this is. if very (it ought to be,
// theres a ton of registers other than these) make this predicate
// branchless and mark with unlikely, then make HandleSpecialRegisterWrite
// noinline yep, its very unlikely. these ORS here are meant to be bitwise
// ors, so that we do not do branching evaluation of the conditions (we will
// almost always take all of the branches)
/* unsigned expr =
(index - XE_GPU_REG_SCRATCH_REG0 < 8) |
(index == XE_GPU_REG_COHER_STATUS_HOST) |
((index - XE_GPU_REG_DC_LUT_RW_INDEX) <=
(XE_GPU_REG_DC_LUT_30_COLOR - XE_GPU_REG_DC_LUT_RW_INDEX));*/
__m128i is_above_lower = _mm_cmpgt_epi16(to_rangecheck, lower_bounds);
__m128i is_below_upper = _mm_cmplt_epi16(to_rangecheck, upper_bounds);
__m128i is_within_range = _mm_and_si128(is_above_lower, is_below_upper);
register_file_->values[index].u32 = value;
uint32_t movmask = static_cast<uint32_t>(_mm_movemask_epi8(is_within_range));
if (!movmask) {
return;
} else {
if (movmask & (1 << 3)) {
if (frame_open_) {
uint32_t float_constant_index =
(index - XE_GPU_REG_SHADER_CONSTANT_000_X) >> 2;
uint64_t float_constant_mask = 1ULL << float_constant_index;
if (float_constant_index >= 256) {
float_constant_index =
static_cast<unsigned char>(float_constant_index);
if (current_float_constant_map_pixel_[float_constant_index >> 6] &
float_constant_mask) { // take advantage of x86
// modulus shift
cbuffer_binding_float_pixel_.up_to_date = false;
}
} else {
if (current_float_constant_map_vertex_[float_constant_index >> 6] &
float_constant_mask) {
cbuffer_binding_float_vertex_.up_to_date = false;
}
}
}
} else if (movmask & (1 << 5)) {
cbuffer_binding_bool_loop_.up_to_date = false;
} else if (movmask & (1 << 1)) {
cbuffer_binding_fetch_.up_to_date = false;
texture_cache_->TextureFetchConstantWritten(
(index - XE_GPU_REG_SHADER_CONSTANT_FETCH_00_0) / 6);
} else {
HandleSpecialRegisterWrite(index, value);
}
}
#else
CommandProcessor::WriteRegister(index, value);
if (index >= XE_GPU_REG_SHADER_CONSTANT_FETCH_00_0 &&
index <= XE_GPU_REG_SHADER_CONSTANT_FETCH_31_5) {
@@ -1693,16 +1761,8 @@ void D3D12CommandProcessor::WriteRegister(uint32_t index, uint32_t value) {
(index - XE_GPU_REG_SHADER_CONSTANT_FETCH_00_0) / 6);
// }
} else {
if (!(cbuf_binding_float_pixel_utd | cbuf_binding_float_vertex_utd |
cbuf_binding_bool_loop_utd)) {
return;
}
if (index >= XE_GPU_REG_SHADER_CONSTANT_000_X &&
index <= XE_GPU_REG_SHADER_CONSTANT_511_W) {
if (!(cbuf_binding_float_pixel_utd | cbuf_binding_float_vertex_utd)) {
return;
}
if (frame_open_) {
uint32_t float_constant_index =
(index - XE_GPU_REG_SHADER_CONSTANT_000_X) >> 2;
@@ -1724,6 +1784,7 @@ void D3D12CommandProcessor::WriteRegister(uint32_t index, uint32_t value) {
cbuffer_binding_bool_loop_.up_to_date = false;
}
}
#endif
}
void D3D12CommandProcessor::WriteRegistersFromMem(uint32_t start_index,
uint32_t* base,
@@ -1733,9 +1794,14 @@ void D3D12CommandProcessor::WriteRegistersFromMem(uint32_t start_index,
D3D12CommandProcessor::WriteRegister(start_index + i, data);
}
}
void D3D12CommandProcessor::WriteRegisterRangeFromRing(xe::RingBuffer* ring,
uint32_t base,
uint32_t num_registers) {
/*
wraparound rarely happens, so its best to hoist this out of
writeregisterrangefromring, and structure the two functions so that this can be
tail called
*/
XE_NOINLINE
void D3D12CommandProcessor::WriteRegisterRangeFromRing_WraparoundCase(
xe::RingBuffer* ring, uint32_t base, uint32_t num_registers) {
// we already brought it into L2 earlier
RingBuffer::ReadRange range =
ring->BeginPrefetchedRead<swcache::PrefetchTag::Level1>(num_registers *
@@ -1747,14 +1813,32 @@ void D3D12CommandProcessor::WriteRegisterRangeFromRing(xe::RingBuffer* ring,
D3D12CommandProcessor::WriteRegistersFromMem(
base, reinterpret_cast<uint32_t*>(const_cast<uint8_t*>(range.first)),
num_regs_firstrange);
if (range.second) {
D3D12CommandProcessor::WriteRegistersFromMem(
base + num_regs_firstrange,
reinterpret_cast<uint32_t*>(const_cast<uint8_t*>(range.second)),
num_registers - num_regs_firstrange);
}
D3D12CommandProcessor::WriteRegistersFromMem(
base + num_regs_firstrange,
reinterpret_cast<uint32_t*>(const_cast<uint8_t*>(range.second)),
num_registers - num_regs_firstrange);
ring->EndRead(range);
}
void D3D12CommandProcessor::WriteRegisterRangeFromRing(xe::RingBuffer* ring,
uint32_t base,
uint32_t num_registers) {
RingBuffer::ReadRange range =
ring->BeginRead(num_registers * sizeof(uint32_t));
XE_LIKELY_IF(!range.second) {
uint32_t num_regs_firstrange =
static_cast<uint32_t>(range.first_length / sizeof(uint32_t));
D3D12CommandProcessor::WriteRegistersFromMem(
base, reinterpret_cast<uint32_t*>(const_cast<uint8_t*>(range.first)),
num_regs_firstrange);
ring->EndRead(range);
} else {
return WriteRegisterRangeFromRing_WraparoundCase(ring, base, num_registers);
}
}
void D3D12CommandProcessor::WriteOneRegisterFromRing(xe::RingBuffer* ring,
uint32_t base,
uint32_t num_times) {
@@ -1768,7 +1852,7 @@ void D3D12CommandProcessor::WriteOneRegisterFromRing(xe::RingBuffer* ring,
base, xe::load_and_swap<uint32_t>(read.first + (sizeof(uint32_t) * i)));
}
if (read.second) {
XE_UNLIKELY_IF (read.second) {
uint32_t second_length = read.second_length / sizeof(uint32_t);
for (uint32_t i = 0; i < second_length; ++i) {
@@ -2791,9 +2875,8 @@ bool D3D12CommandProcessor::IssueCopy() {
// chrispy: this memcpy needs to be optimized as much as possible
auto physaddr = memory_->TranslatePhysical(written_address);
dma::vastcpy(physaddr, (uint8_t*)readback_mapping,
written_length);
// XEDmaCpy(physaddr, readback_mapping, written_length);
dma::vastcpy(physaddr, (uint8_t*)readback_mapping, written_length);
// XEDmaCpy(physaddr, readback_mapping, written_length);
D3D12_RANGE readback_write_range = {};
readback_buffer->Unmap(0, &readback_write_range);
}
@@ -4606,12 +4689,12 @@ ID3D12Resource* D3D12CommandProcessor::RequestReadbackBuffer(uint32_t size) {
if (size == 0) {
return nullptr;
}
#if 0
#if 0
if (readback_available_) {
GetDMAC()->WaitJobDone(readback_available_);
readback_available_ = 0;
}
#endif
#endif
size = xe::align(size, kReadbackBufferSizeIncrement);
if (size > readback_buffer_size_) {
const ui::d3d12::D3D12Provider& provider = GetD3D12Provider();

8
src/xenia/gpu/d3d12/d3d12_command_processor.h
View File

@@ -213,6 +213,11 @@ class D3D12CommandProcessor final : public CommandProcessor {
XE_FORCEINLINE
virtual void WriteRegisterRangeFromRing(xe::RingBuffer* ring, uint32_t base,
uint32_t num_registers) override;
XE_NOINLINE
void WriteRegisterRangeFromRing_WraparoundCase(xe::RingBuffer* ring,
uint32_t base,
uint32_t num_registers);
XE_FORCEINLINE
virtual void WriteOneRegisterFromRing(xe::RingBuffer* ring, uint32_t base,
uint32_t num_times) override;
@@ -614,7 +619,8 @@ class D3D12CommandProcessor final : public CommandProcessor {
uint32_t current_graphics_root_up_to_date_;
// System shader constants.
DxbcShaderTranslator::SystemConstants system_constants_;
alignas(XE_HOST_CACHE_LINE_SIZE)
DxbcShaderTranslator::SystemConstants system_constants_;
// Float constant usage masks of the last draw call.
// chrispy: make sure accesses to these cant cross cacheline boundaries

12
src/xenia/gpu/d3d12/pipeline_cache.cc
View File

@@ -427,7 +427,9 @@ void PipelineCache::InitializeShaderStorage(
++shader_translation_threads_busy;
break;
}
shader_to_translate->AnalyzeUcode(ucode_disasm_buffer);
if (!shader_to_translate->is_ucode_analyzed()) {
shader_to_translate->AnalyzeUcode(ucode_disasm_buffer);
}
// Translate each needed modification on this thread after performing
// modification-independent analysis of the whole shader.
uint64_t ucode_data_hash = shader_to_translate->ucode_data_hash();
@@ -980,7 +982,9 @@ bool PipelineCache::ConfigurePipeline(
xenos::VertexShaderExportMode::kPosition2VectorsEdgeKill);
assert_false(register_file_.Get<reg::SQ_PROGRAM_CNTL>().gen_index_vtx);
if (!vertex_shader->is_translated()) {
vertex_shader->shader().AnalyzeUcode(ucode_disasm_buffer_);
if (!vertex_shader->shader().is_ucode_analyzed()) {
vertex_shader->shader().AnalyzeUcode(ucode_disasm_buffer_);
}
if (!TranslateAnalyzedShader(*shader_translator_, *vertex_shader,
dxbc_converter_, dxc_utils_, dxc_compiler_)) {
XELOGE("Failed to translate the vertex shader!");
@@ -1004,7 +1008,9 @@ bool PipelineCache::ConfigurePipeline(
}
if (pixel_shader != nullptr) {
if (!pixel_shader->is_translated()) {
pixel_shader->shader().AnalyzeUcode(ucode_disasm_buffer_);
if (!pixel_shader->shader().is_ucode_analyzed()) {
pixel_shader->shader().AnalyzeUcode(ucode_disasm_buffer_);
}
if (!TranslateAnalyzedShader(*shader_translator_, *pixel_shader,
dxbc_converter_, dxc_utils_,
dxc_compiler_)) {

4
src/xenia/gpu/d3d12/pipeline_cache.h
View File

@@ -71,7 +71,9 @@ class PipelineCache {
const uint32_t* host_address, uint32_t dword_count);
// Analyze shader microcode on the translator thread.
void AnalyzeShaderUcode(Shader& shader) {
shader.AnalyzeUcode(ucode_disasm_buffer_);
if (!shader.is_ucode_analyzed()) {
shader.AnalyzeUcode(ucode_disasm_buffer_);
}
}
// Retrieves the shader modification for the current state. The shader must

48
src/xenia/gpu/draw_util.h
View File

@@ -53,6 +53,26 @@ inline bool IsPrimitiveLine(const RegisterFile& regs) {
regs.Get<reg::VGT_DRAW_INITIATOR>().prim_type);
}
constexpr uint32_t EncodeIsPrimitivePolygonalTable() {
unsigned result = 0;
#define TRUEFOR(x) \
result |= 1U << static_cast<uint32_t>(xenos::PrimitiveType::x)
TRUEFOR(kTriangleList);
TRUEFOR(kTriangleFan);
TRUEFOR(kTriangleStrip);
TRUEFOR(kTriangleWithWFlags);
TRUEFOR(kQuadList);
TRUEFOR(kQuadStrip);
TRUEFOR(kPolygon);
#undef TRUEFOR
// TODO(Triang3l): Investigate how kRectangleList should be treated - possibly
// actually drawn as two polygons on the console, however, the current
// geometry shader doesn't care about the winding order - allowing backface
// culling for rectangles currently breaks 4D53082D.
return result;
}
// Polygonal primitive types (not including points and lines) are rasterized as
// triangles, have front and back faces, and also support face culling and fill
// modes (polymode_front_ptype, polymode_back_ptype). Other primitive types are
@@ -61,6 +81,7 @@ inline bool IsPrimitiveLine(const RegisterFile& regs) {
// GL_FRONT_AND_BACK, points and lines are still drawn), and may in some cases
// use the "para" registers instead of "front" or "back" (for "parallelogram" -
// like poly_offset_para_enable).
XE_FORCEINLINE
constexpr bool IsPrimitivePolygonal(bool vgt_output_path_is_tessellation_enable,
xenos::PrimitiveType type) {
if (vgt_output_path_is_tessellation_enable &&
@@ -71,26 +92,15 @@ constexpr bool IsPrimitivePolygonal(bool vgt_output_path_is_tessellation_enable,
// enough.
return true;
}
switch (type) {
case xenos::PrimitiveType::kTriangleList:
case xenos::PrimitiveType::kTriangleFan:
case xenos::PrimitiveType::kTriangleStrip:
case xenos::PrimitiveType::kTriangleWithWFlags:
case xenos::PrimitiveType::kQuadList:
case xenos::PrimitiveType::kQuadStrip:
case xenos::PrimitiveType::kPolygon:
return true;
default:
break;
}
// TODO(Triang3l): Investigate how kRectangleList should be treated - possibly
// actually drawn as two polygons on the console, however, the current
// geometry shader doesn't care about the winding order - allowing backface
// culling for rectangles currently breaks 4D53082D.
return false;
}
// chrispy: expensive jumptable, use bit table instead
inline bool IsPrimitivePolygonal(const RegisterFile& regs) {
constexpr uint32_t primitive_polygonal_table =
EncodeIsPrimitivePolygonalTable();
return (primitive_polygonal_table & (1U << static_cast<uint32_t>(type))) != 0;
}
XE_FORCEINLINE
bool IsPrimitivePolygonal(const RegisterFile& regs) {
return IsPrimitivePolygonal(
regs.Get<reg::VGT_OUTPUT_PATH_CNTL>().path_select ==
xenos::VGTOutputPath::kTessellationEnable,

4
src/xenia/gpu/dxbc_shader_translator.cc
View File

@@ -94,7 +94,9 @@ std::vector<uint8_t> DxbcShaderTranslator::CreateDepthOnlyPixelShader() {
// TODO(Triang3l): Handle in a nicer way (is_depth_only_pixel_shader_ is a
// leftover from when a Shader object wasn't used during translation).
Shader shader(xenos::ShaderType::kPixel, 0, nullptr, 0);
shader.AnalyzeUcode(instruction_disassembly_buffer_);
if (!shader.is_ucode_analyzed()) {
shader.AnalyzeUcode(instruction_disassembly_buffer_);
}
Shader::Translation& translation = *shader.GetOrCreateTranslation(0);
TranslateAnalyzedShader(translation);
is_depth_only_pixel_shader_ = false;

12
src/xenia/gpu/graphics_system.cc
View File

@@ -50,7 +50,11 @@ __declspec(dllexport) uint32_t AmdPowerXpressRequestHighPerformance = 1;
} // extern "C"
#endif // XE_PLATFORM_WIN32
GraphicsSystem::GraphicsSystem() : vsync_worker_running_(false) {}
GraphicsSystem::GraphicsSystem() : vsync_worker_running_(false) {
register_file_ = reinterpret_cast<RegisterFile*>(memory::AllocFixed(
nullptr, sizeof(RegisterFile), memory::AllocationType::kReserveCommit,
memory::PageAccess::kReadWrite));
}
GraphicsSystem::~GraphicsSystem() = default;
@@ -198,13 +202,13 @@ uint32_t GraphicsSystem::ReadRegister(uint32_t addr) {
// maximum [width(0x0FFF), height(0x0FFF)]
return 0x050002D0;
default:
if (!register_file_.IsValidRegister(r)) {
if (!register_file()->IsValidRegister(r)) {
XELOGE("GPU: Read from unknown register ({:04X})", r);
}
}
assert_true(r < RegisterFile::kRegisterCount);
return register_file_.values[r].u32;
return register_file()->values[r].u32;
}
void GraphicsSystem::WriteRegister(uint32_t addr, uint32_t value) {
@@ -222,7 +226,7 @@ void GraphicsSystem::WriteRegister(uint32_t addr, uint32_t value) {
}
assert_true(r < RegisterFile::kRegisterCount);
register_file_.values[r].u32 = value;
this->register_file()->values[r].u32 = value;
}
void GraphicsSystem::InitializeRingBuffer(uint32_t ptr, uint32_t size_log2) {

4
src/xenia/gpu/graphics_system.h
View File

@@ -58,7 +58,7 @@ class GraphicsSystem {
// from a device loss.
void OnHostGpuLossFromAnyThread(bool is_responsible);
RegisterFile* register_file() { return &register_file_; }
RegisterFile* register_file() { return register_file_; }
CommandProcessor* command_processor() const {
return command_processor_.get();
}
@@ -112,7 +112,7 @@ class GraphicsSystem {
std::atomic<bool> vsync_worker_running_;
kernel::object_ref<kernel::XHostThread> vsync_worker_thread_;
RegisterFile register_file_;
RegisterFile* register_file_;
std::unique_ptr<CommandProcessor> command_processor_;
bool paused_ = false;

73
src/xenia/gpu/texture_info.h
View File

@@ -10,17 +10,86 @@
#ifndef XENIA_GPU_TEXTURE_INFO_H_
#define XENIA_GPU_TEXTURE_INFO_H_
#include <array>
#include <cstring>
#include <memory>
#include "xenia/base/assert.h"
#include "xenia/gpu/xenos.h"
namespace xe {
namespace gpu {
#if XE_ARCH_AMD64 == 1
struct GetBaseFormatHelper {
uint64_t indexer_;
// chrispy: todo, can encode deltas or a SHIFT+ADD for remapping the input
// format to the base, the shuffle lookup isnt great
std::array<int8_t, 16> remap_;
};
constexpr GetBaseFormatHelper PrecomputeGetBaseFormatTable() {
#define R(x, y) xenos::TextureFormat::x, xenos::TextureFormat::y
constexpr xenos::TextureFormat entries[] = {
R(k_16_EXPAND, k_16_FLOAT),
R(k_16_16_EXPAND, k_16_16_FLOAT),
R(k_16_16_16_16_EXPAND, k_16_16_16_16_FLOAT),
R(k_8_8_8_8_AS_16_16_16_16, k_8_8_8_8),
R(k_DXT1_AS_16_16_16_16, k_DXT1),
R(k_DXT2_3_AS_16_16_16_16, k_DXT2_3),
R(k_DXT4_5_AS_16_16_16_16, k_DXT4_5),
R(k_2_10_10_10_AS_16_16_16_16, k_2_10_10_10),
R(k_10_11_11_AS_16_16_16_16, k_10_11_11),
R(k_11_11_10_AS_16_16_16_16, k_11_11_10),
R(k_8_8_8_8_GAMMA_EDRAM, k_8_8_8_8)};
#undef R
uint64_t need_remap_table = 0ULL;
constexpr unsigned num_entries = sizeof(entries) / sizeof(entries[0]);
for (unsigned i = 0; i < num_entries / 2; ++i) {
need_remap_table |= 1ULL << static_cast<uint32_t>(entries[i * 2]);
}
std::array<int8_t, 16> remap{0};
for (unsigned i = 0; i < num_entries / 2; ++i) {
remap[i] = static_cast<int8_t>(static_cast<uint32_t>(entries[(i * 2) + 1]));
}
return GetBaseFormatHelper{need_remap_table, remap};
}
inline xenos::TextureFormat GetBaseFormat(xenos::TextureFormat texture_format) {
constexpr GetBaseFormatHelper helper = PrecomputeGetBaseFormatTable();
constexpr uint64_t indexer_table = helper.indexer_;
constexpr std::array<int8_t, 16> table = helper.remap_;
uint64_t format_mask = 1ULL << static_cast<uint32_t>(texture_format);
if ((indexer_table & format_mask)) {
uint64_t trailing_mask = format_mask - 1ULL;
uint64_t trailing_bits = indexer_table & trailing_mask;
uint32_t sparse_index = xe::bit_count(trailing_bits);
__m128i index_in_low =
_mm_cvtsi32_si128(static_cast<int>(sparse_index) | 0x80808000);
__m128i new_format_low = _mm_shuffle_epi8(
_mm_setr_epi8(table[0], table[1], table[2], table[3], table[4],
table[5], table[6], table[7], table[8], table[9],
table[10], table[11], table[12], 0, 0, 0),
index_in_low);
uint32_t prelaundered =
static_cast<uint32_t>(_mm_cvtsi128_si32(new_format_low));
return *reinterpret_cast<xenos::TextureFormat*>(&prelaundered);
} else {
return texture_format;
}
}
#else
inline xenos::TextureFormat GetBaseFormat(xenos::TextureFormat texture_format) {
// These formats are used for resampling textures / gamma control.
// 11 entries
switch (texture_format) {
case xenos::TextureFormat::k_16_EXPAND:
return xenos::TextureFormat::k_16_FLOAT;
@@ -50,7 +119,7 @@ inline xenos::TextureFormat GetBaseFormat(xenos::TextureFormat texture_format) {
return texture_format;
}
#endif
inline size_t GetTexelSize(xenos::TextureFormat format) {
switch (format) {
case xenos::TextureFormat::k_1_5_5_5: