fabi/Xenia-Canary
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Normalizing tests.

Browse Source
This commit is contained in:
Ben Vanik
2015-08-18 00:27:27 -07:00
parent c67e47a076
commit c6b941a709
2 changed files with 36 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
src/xenia/cpu/frontend/testing/instr_rldicl.s
View File

@@ -1,9 +1,9 @@
.macro make_test_constant dest .macro make_full_test_constant dest, a, b, c, d
lis \dest, 0x0123 lis \dest, \a
ori \dest, \dest, 0x4567 ori \dest, \dest, \b
sldi \dest, \dest, 32 sldi \dest, \dest, 32
lis r3, 0x89AB lis r3, \c
ori r3, r3, 0xCDEF ori r3, r3, \d
clrldi r3, r3, 32 clrldi r3, r3, 32
or \dest, \dest, r3 or \dest, \dest, r3
.endm .endm
@@ -16,7 +16,7 @@ test_rldicl_1:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_1_constant: test_rldicl_1_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 24, 0 rldicl r3, r4, 24, 0
blr blr
#_ REGISTER_OUT r3 0x6789abcdef012345 #_ REGISTER_OUT r3 0x6789abcdef012345
@@ -30,7 +30,7 @@ test_rldicl_2:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_2_constant: test_rldicl_2_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 24, 8 rldicl r3, r4, 24, 8
blr blr
#_ REGISTER_OUT r3 0x0089abcdef012345 #_ REGISTER_OUT r3 0x0089abcdef012345
@@ -44,7 +44,7 @@ test_rldicl_3:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_3_constant: test_rldicl_3_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 24, 63 rldicl r3, r4, 24, 63
blr blr
#_ REGISTER_OUT r3 0x0000000000000001 #_ REGISTER_OUT r3 0x0000000000000001
@@ -58,7 +58,7 @@ test_rldicl_4:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_4_constant: test_rldicl_4_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 0, 0 rldicl r3, r4, 0, 0
blr blr
#_ REGISTER_OUT r3 0x0123456789abcdef #_ REGISTER_OUT r3 0x0123456789abcdef
@@ -72,7 +72,7 @@ test_rldicl_5:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_5_constant: test_rldicl_5_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 0, 63 rldicl r3, r4, 0, 63
blr blr
#_ REGISTER_OUT r3 0x0000000000000001 #_ REGISTER_OUT r3 0x0000000000000001
@@ -86,7 +86,7 @@ test_rldicl_6:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_6_constant: test_rldicl_6_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 0, 8 rldicl r3, r4, 0, 8
blr blr
#_ REGISTER_OUT r3 0x0023456789abcdef #_ REGISTER_OUT r3 0x0023456789abcdef
@@ -100,7 +100,7 @@ test_rldicl_7:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_7_constant: test_rldicl_7_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 63, 0 rldicl r3, r4, 63, 0
blr blr
#_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7 #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
@@ -114,7 +114,7 @@ test_rldicl_8:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_8_constant: test_rldicl_8_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 63, 63 rldicl r3, r4, 63, 63
blr blr
#_ REGISTER_OUT r3 0x0000000000000001 #_ REGISTER_OUT r3 0x0000000000000001
@@ -128,7 +128,7 @@ test_rldicl_9:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_9_constant: test_rldicl_9_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 31, 0 rldicl r3, r4, 31, 0
blr blr
#_ REGISTER_OUT r3 0xc4d5e6f78091a2b3 #_ REGISTER_OUT r3 0xc4d5e6f78091a2b3
@@ -158,7 +158,7 @@ test_srdi_1:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_srdi_1_constant: test_srdi_1_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1 li r3, -1
srdi r3, r3, 0 srdi r3, r3, 0
srdi r4, r4, 0 srdi r4, r4, 0
@@ -176,7 +176,7 @@ test_srdi_2:
#_ REGISTER_OUT r4 0x0091a2b3c4d5e6f7 #_ REGISTER_OUT r4 0x0091a2b3c4d5e6f7
test_srdi_2_constant: test_srdi_2_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1 li r3, -1
srdi r3, r3, 1 srdi r3, r3, 1
srdi r4, r4, 1 srdi r4, r4, 1
@@ -194,7 +194,7 @@ test_srdi_3:
#_ REGISTER_OUT r4 0x0000000001234567 #_ REGISTER_OUT r4 0x0000000001234567
test_srdi_3_constant: test_srdi_3_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1 li r3, -1
srdi r3, r3, 32 srdi r3, r3, 32
srdi r4, r4, 32 srdi r4, r4, 32
@@ -212,7 +212,7 @@ test_srdi_4:
#_ REGISTER_OUT r4 0x0000000000000000 #_ REGISTER_OUT r4 0x0000000000000000
test_srdi_4_constant: test_srdi_4_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1 li r3, -1
srdi r3, r3, 63 srdi r3, r3, 63
srdi r4, r4, 63 srdi r4, r4, 63

36
src/xenia/cpu/frontend/testing/instr_rldicr.s
View File

@@ -1,9 +1,9 @@
.macro make_test_constant dest .macro make_full_test_constant dest, a, b, c, d
lis \dest, 0x0123 lis \dest, \a
ori \dest, \dest, 0x4567 ori \dest, \dest, \b
sldi \dest, \dest, 32 sldi \dest, \dest, 32
lis r3, 0x89AB lis r3, \c
ori r3, r3, 0xCDEF ori r3, r3, \d
clrldi r3, r3, 32 clrldi r3, r3, 32
or \dest, \dest, r3 or \dest, \dest, r3
.endm .endm
@@ -16,7 +16,7 @@ test_rldicr_1:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_1_constant: test_rldicr_1_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 24, 0 rldicr r3, r4, 24, 0
blr blr
#_ REGISTER_OUT r3 0x0000000000000000 #_ REGISTER_OUT r3 0x0000000000000000
@@ -30,7 +30,7 @@ test_rldicr_2:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_2_constant: test_rldicr_2_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 24, 8 rldicr r3, r4, 24, 8
blr blr
#_ REGISTER_OUT r3 0x6780000000000000 #_ REGISTER_OUT r3 0x6780000000000000
@@ -44,7 +44,7 @@ test_rldicr_3:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_3_constant: test_rldicr_3_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 24, 63 rldicr r3, r4, 24, 63
blr blr
#_ REGISTER_OUT r3 0x6789abcdef012345 #_ REGISTER_OUT r3 0x6789abcdef012345
@@ -58,7 +58,7 @@ test_rldicr_4:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_4_constant: test_rldicr_4_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 0, 0 rldicr r3, r4, 0, 0
blr blr
#_ REGISTER_OUT r3 0x0000000000000000 #_ REGISTER_OUT r3 0x0000000000000000
@@ -72,7 +72,7 @@ test_rldicr_5:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_5_constant: test_rldicr_5_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 0, 63 rldicr r3, r4, 0, 63
blr blr
#_ REGISTER_OUT r3 0x0123456789abcdef #_ REGISTER_OUT r3 0x0123456789abcdef
@@ -86,7 +86,7 @@ test_rldicr_6:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_6_constant: test_rldicr_6_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 0, 8 rldicr r3, r4, 0, 8
blr blr
#_ REGISTER_OUT r3 0x0100000000000000 #_ REGISTER_OUT r3 0x0100000000000000
@@ -100,7 +100,7 @@ test_rldicr_7:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_7_constant: test_rldicr_7_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 63, 0 rldicr r3, r4, 63, 0
blr blr
#_ REGISTER_OUT r3 0x8000000000000000 #_ REGISTER_OUT r3 0x8000000000000000
@@ -114,7 +114,7 @@ test_rldicr_8:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_8_constant: test_rldicr_8_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 63, 63 rldicr r3, r4, 63, 63
blr blr
#_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7 #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
@@ -128,7 +128,7 @@ test_rldicr_9:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_9_constant: test_rldicr_9_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 31, 0 rldicr r3, r4, 31, 0
blr blr
#_ REGISTER_OUT r3 0x8000000000000000 #_ REGISTER_OUT r3 0x8000000000000000
@@ -144,7 +144,7 @@ test_sldi_1:
#_ REGISTER_OUT r4 0x0123456789ABCDEF #_ REGISTER_OUT r4 0x0123456789ABCDEF
test_sldi_1_constant: test_sldi_1_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1 li r3, -1
sldi r3, r3, 0 sldi r3, r3, 0
sldi r4, r4, 0 sldi r4, r4, 0
@@ -162,7 +162,7 @@ test_sldi_2:
#_ REGISTER_OUT r4 0x02468acf13579bde #_ REGISTER_OUT r4 0x02468acf13579bde
test_sldi_2_constant: test_sldi_2_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1 li r3, -1
sldi r3, r3, 1 sldi r3, r3, 1
sldi r4, r4, 1 sldi r4, r4, 1
@@ -180,7 +180,7 @@ test_sldi_3:
#_ REGISTER_OUT r4 0x89abcdef00000000 #_ REGISTER_OUT r4 0x89abcdef00000000
test_sldi_3_constant: test_sldi_3_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1 li r3, -1
sldi r3, r3, 32 sldi r3, r3, 32
sldi r4, r4, 32 sldi r4, r4, 32
@@ -198,7 +198,7 @@ test_sldi_4:
#_ REGISTER_OUT r4 0x8000000000000000 #_ REGISTER_OUT r4 0x8000000000000000
test_sldi_4_constant: test_sldi_4_constant:
make_test_constant r4 make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1 li r3, -1
sldi r3, r3, 63 sldi r3, r3, 63
sldi r4, r4, 63 sldi r4, r4, 63