[Vulkan] Blend and depth/stencil state, small pipeline cleanup

src/xenia/gpu/spirv_shader_translator.h

@@ -34,7 +34,7 @@ class SpirvShaderTranslator : public ShaderTranslator {
     // TODO(Triang3l): Change to 0xYYYYMMDD once it's out of the rapid
     // prototyping stage (easier to do small granular updates with an
     // incremental counter).
-    static constexpr uint32_t kVersion = 2;
+    static constexpr uint32_t kVersion = 3;
 
     struct {
       // Dynamically indexable register count from SQ_PROGRAM_CNTL.
@@ -46,6 +46,11 @@ class SpirvShaderTranslator : public ShaderTranslator {
     struct PixelShaderModification {
       // Dynamically indexable register count from SQ_PROGRAM_CNTL.
       uint32_t dynamic_addressable_register_count : 8;
+      // Color outputs removed from the shader to implement a zero color write
+      // mask when independent blending (and thus independent write masks) is
+      // not supported without switching to a render pass with some attachments
+      // actually excluded.
+      uint32_t color_outputs_disabled : 4;
     } pixel;
     uint64_t value = 0;