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[CPU] vupkd3d: NaN on negative overflow and tests

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Triang3l
2018-06-11 21:31:30 +03:00
parent 03099bd6c0
commit c89cc6a229
4 changed files with 41 additions and 0 deletions
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25
src/xenia/cpu/ppc/testing/instr_vupkd3d128.s
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@@ -32,6 +32,12 @@ test_vupkd3d128_short2_2:
.long 0x18641FF0
blr
#_ REGISTER_OUT v3 [40407FFF, 403FF333, 00000000, 3f800000]
test_vupkd3d128_short2_3:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00008000]
# vupkd3d128 v3, v3, 1
.long 0x18641FF0
blr
#_ REGISTER_OUT v3 [40400000, 7FC00000, 00000000, 3f800000]
test_vupkd3d128_short4_0:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, 7FFFFFFF, 007FFFF8]
@@ -53,3 +59,22 @@ test_vupkd3d128_float16_4_0:
.long 0x18741FF0
blr
#_ REGISTER_OUT v3 [3F000000, bf002000, 3f004000, bf006000]
test_vupkd3d128_uint_2101010_0:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 400001FF]
# vupkd3d128 v3, v3, 2
.long 0x18681FF0
blr
#_ REGISTER_OUT v3 [404001FF, 40400000, 40400000, 3F800001]
test_vupkd3d128_uint_2101010_1:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 40000201]
# vupkd3d128 v3, v3, 2
.long 0x18681FF0
blr
#_ REGISTER_OUT v3 [403FFE01, 40400000, 40400000, 3F800001]
test_vupkd3d128_uint_2101010_2:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 40000200]
# vupkd3d128 v3, v3, 2
.long 0x18681FF0
blr
#_ REGISTER_OUT v3 [7FC00000, 40400000, 40400000, 3F800001]