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Huge set of performance improvements, combined with an architecture specific build and clang-cl users have reported absurd gains over master for some gains, in the range 50%-90%

Browse Source 
But for normal msvc builds i would put it at around 30-50%
Added per-xexmodule caching of information per instruction, can be used to remember what code needs compiling at start up
Record what guest addresses wrote mmio and backpropagate that to future runs, eliminating dependence on exception trapping. this makes many games like h3 actually tolerable to run under a debugger
fixed a number of errors where temporaries were being passed by reference/pointer
Can now be compiled with clang-cl 14.0.1, requires -Werror off though and some other solution/project changes.
Added macros wrapping compiler extensions like noinline, forceinline, __expect, and cold.
Removed the "global lock" in guest code completely. It does not properly emulate the behavior of mfmsrd/mtmsr and it seriously cripples amd cpus. Removing this yielded around a 3x speedup in Halo Reach for me.
Disabled the microprofiler for now. The microprofiler has a huge performance cost associated with it. Developers can re-enable it in the base/profiling header if they really need it
Disable the trace writer in release builds. despite just returning after checking if the file was open the trace functions were consuming about 0.60% cpu time total
Add IsValidReg, GetRegisterInfo is a huge (about 45k) branching function and using that to check if a register was valid consumed a significant chunk of time
Optimized RingBuffer::ReadAndSwap and RingBuffer::read_count. This gave us the largest overall boost in performance. The memcpies were unnecessary and one of them was always a no-op
Added simplification rules for multiplicative patterns like (x+x), (x<<1)+x
For the most frequently called win32 functions i added code to call their underlying NT implementations, which lets us skip a lot of MS code we don't care about/isnt relevant to our usecases
^this can be toggled off in the platform_win header
handle indirect call true with constant function pointer, was occurring in h3
lookup host format swizzle in denser array
by default, don't check if a gpu register is unknown, instead just check if its out of range. controlled by a cvar
^looking up whether its known or not took approx 0.3% cpu time
Changed some things in /cpu to make the project UNITYBUILD friendly
The timer thread was spinning way too much and consuming a ton of cpu, changed it to use a blocking wait instead
tagged some conditions as XE_UNLIKELY/LIKELY based on profiler feedback (will only affect clang builds)
Shifted around some code in CommandProcessor::WriteRegister based on how frequently it was executed
added support for docdecaduple precision floating point so that we can represent our performance gains numerically
tons of other stuff im probably forgetting
This commit is contained in:
chss95cs@gmail.com
2022-08-13 12:59:00 -07:00
parent 2f59487bf3
commit cb85fe401c
49 changed files with 1462 additions and 483 deletions
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137
src/xenia/cpu/backend/x64/x64_seq_memory.cc
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@@ -18,7 +18,7 @@
#include "xenia/cpu/backend/x64/x64_op.h"
#include "xenia/cpu/backend/x64/x64_tracers.h"
#include "xenia/cpu/ppc/ppc_context.h"
#include "xenia/cpu/processor.h"
DEFINE_bool(
elide_e0_check, false,
"Eliminate e0 check on some memory accesses, like to r13(tls) or r1(sp)",
@@ -27,6 +27,10 @@ DEFINE_bool(enable_rmw_context_merging, false,
"Permit merging read-modify-write HIR instr sequences together "
"into x86 instructions that use a memory operand.",
"x64");
DEFINE_bool(emit_mmio_aware_stores_for_recorded_exception_addresses, true,
"Uses info gathered via record_mmio_access_exceptions to emit "
"special stores that are faster than trapping the exception",
"CPU");
namespace xe {
namespace cpu {
@@ -965,6 +969,21 @@ struct STORE_MMIO_I32
}
};
EMITTER_OPCODE_TABLE(OPCODE_STORE_MMIO, STORE_MMIO_I32);
// according to triangle we dont support mmio reads atm so no point in
// implementing this for them
static bool IsPossibleMMIOInstruction(X64Emitter& e, const hir::Instr* i) {
if (!cvars::emit_mmio_aware_stores_for_recorded_exception_addresses) {
return false;
}
uint32_t guestaddr = i->GuestAddressFor();
if (!guestaddr) {
return false;
}
auto flags = e.GuestModule()->GetInstructionAddressFlags(guestaddr);
return flags && flags->accessed_mmio;
}
// ============================================================================
// OPCODE_LOAD_OFFSET
@@ -1030,6 +1049,28 @@ struct LOAD_OFFSET_I64
EMITTER_OPCODE_TABLE(OPCODE_LOAD_OFFSET, LOAD_OFFSET_I8, LOAD_OFFSET_I16,
LOAD_OFFSET_I32, LOAD_OFFSET_I64);
template <typename T, bool swap>
static void MMIOAwareStore(void* _ctx, unsigned int guestaddr, T value) {
if (swap) {
value = xe::byte_swap(value);
}
if (guestaddr >= 0xE0000000) {
guestaddr += 0x1000;
}
auto ctx = reinterpret_cast<ppc::PPCContext*>(_ctx);
auto gaddr = ctx->processor->memory()->LookupVirtualMappedRange(guestaddr);
if (!gaddr) {
*reinterpret_cast<T*>(ctx->virtual_membase + guestaddr) = value;
} else {
value = xe::byte_swap(value); /*
was having issues, found by comparing the values used with exceptions
to these that we were reversed...
*/
gaddr->write(nullptr, gaddr->callback_context, guestaddr, value);
}
}
// ============================================================================
// OPCODE_STORE_OFFSET
// ============================================================================
@@ -1038,6 +1079,7 @@ struct STORE_OFFSET_I8
I<OPCODE_STORE_OFFSET, VoidOp, I64Op, I64Op, I8Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) {
auto addr = ComputeMemoryAddressOffset(e, i.src1, i.src2);
if (i.src3.is_constant) {
e.mov(e.byte[addr], i.src3.constant());
} else {
@@ -1076,23 +1118,48 @@ struct STORE_OFFSET_I32
: Sequence<STORE_OFFSET_I32,
I<OPCODE_STORE_OFFSET, VoidOp, I64Op, I64Op, I32Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) {
auto addr = ComputeMemoryAddressOffset(e, i.src1, i.src2);
if (i.instr->flags & LoadStoreFlags::LOAD_STORE_BYTE_SWAP) {
assert_false(i.src3.is_constant);
if (e.IsFeatureEnabled(kX64EmitMovbe)) {
e.movbe(e.dword[addr], i.src3);
} else {
assert_always("not implemented");
if (IsPossibleMMIOInstruction(e, i.instr)) {
void* addrptr = (void*)&MMIOAwareStore<uint32_t, false>;
if (i.instr->flags & LoadStoreFlags::LOAD_STORE_BYTE_SWAP) {
addrptr = (void*)&MMIOAwareStore<uint32_t, true>;
}
if (i.src1.is_constant) {
e.mov(e.GetNativeParam(0).cvt32(), i.src1.constant());
} else {
e.mov(e.GetNativeParam(0).cvt32(), i.src1.reg().cvt32());
}
if (i.src2.is_constant) {
e.add(e.GetNativeParam(0).cvt32(), (uint32_t)i.src2.constant());
} else {
e.add(e.GetNativeParam(0).cvt32(), i.src2);
}
} else {
if (i.src3.is_constant) {
if (i.src3.constant() == 0 && e.CanUseMembaseLow32As0()) {
e.mov(e.dword[addr], e.GetMembaseReg().cvt32());
e.mov(e.GetNativeParam(1).cvt32(), i.src3.constant());
} else {
e.mov(e.GetNativeParam(1).cvt32(), i.src3);
}
e.CallNativeSafe(addrptr);
} else {
auto addr = ComputeMemoryAddressOffset(e, i.src1, i.src2);
if (i.instr->flags & LoadStoreFlags::LOAD_STORE_BYTE_SWAP) {
assert_false(i.src3.is_constant);
if (e.IsFeatureEnabled(kX64EmitMovbe)) {
e.movbe(e.dword[addr], i.src3);
} else {
e.mov(e.dword[addr], i.src3.constant());
assert_always("not implemented");
}
} else {
e.mov(e.dword[addr], i.src3);
if (i.src3.is_constant) {
if (i.src3.constant() == 0 && e.CanUseMembaseLow32As0()) {
e.mov(e.dword[addr], e.GetMembaseReg().cvt32());
} else {
e.mov(e.dword[addr], i.src3.constant());
}
} else {
e.mov(e.dword[addr], i.src3);
}
}
}
}
@@ -1290,23 +1357,43 @@ struct STORE_I16 : Sequence<STORE_I16, I<OPCODE_STORE, VoidOp, I64Op, I16Op>> {
};
struct STORE_I32 : Sequence<STORE_I32, I<OPCODE_STORE, VoidOp, I64Op, I32Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) {
auto addr = ComputeMemoryAddress(e, i.src1);
if (i.instr->flags & LoadStoreFlags::LOAD_STORE_BYTE_SWAP) {
assert_false(i.src2.is_constant);
if (e.IsFeatureEnabled(kX64EmitMovbe)) {
e.movbe(e.dword[addr], i.src2);
} else {
assert_always("not implemented");
if (IsPossibleMMIOInstruction(e, i.instr)) {
void* addrptr = (void*)&MMIOAwareStore<uint32_t, false>;
if (i.instr->flags & LoadStoreFlags::LOAD_STORE_BYTE_SWAP) {
addrptr = (void*)&MMIOAwareStore<uint32_t, true>;
}
} else {
if (i.src2.is_constant) {
e.mov(e.dword[addr], i.src2.constant());
if (i.src1.is_constant) {
e.mov(e.GetNativeParam(0).cvt32(), (uint32_t)i.src1.constant());
} else {
e.mov(e.dword[addr], i.src2);
e.mov(e.GetNativeParam(0).cvt32(), i.src1.reg().cvt32());
}
if (i.src2.is_constant) {
e.mov(e.GetNativeParam(1).cvt32(), i.src2.constant());
} else {
e.mov(e.GetNativeParam(1).cvt32(), i.src2);
}
e.CallNativeSafe(addrptr);
} else {
auto addr = ComputeMemoryAddress(e, i.src1);
if (i.instr->flags & LoadStoreFlags::LOAD_STORE_BYTE_SWAP) {
assert_false(i.src2.is_constant);
if (e.IsFeatureEnabled(kX64EmitMovbe)) {
e.movbe(e.dword[addr], i.src2);
} else {
assert_always("not implemented");
}
} else {
if (i.src2.is_constant) {
e.mov(e.dword[addr], i.src2.constant());
} else {
e.mov(e.dword[addr], i.src2);
}
}
}
if (IsTracingData()) {
addr = ComputeMemoryAddress(e, i.src1);
auto addr = ComputeMemoryAddress(e, i.src1);
e.mov(e.GetNativeParam(1).cvt32(), e.dword[addr]);
e.lea(e.GetNativeParam(0), e.ptr[addr]);
e.CallNative(reinterpret_cast<void*>(TraceMemoryStoreI32));