Fixing CR update for divwu/divdu/mulhwu.

src/xenia/cpu/ppc/testing/instr_divdu.s

@@ -163,3 +163,21 @@ test_divdu_9_constant:
   #_ REGISTER_OUT r3 0
   #_ REGISTER_OUT r4 0x8000000000000000
   #_ REGISTER_OUT r5 -1
+
+test_divdu_10:
+  #_ REGISTER_IN r0 0x1
+  #_ REGISTER_IN r3 0xFFFFFFFF
+  divdu. r0, r3, r0
+  blr
+  #_ REGISTER_OUT r0 0xFFFFFFFF
+  #_ REGISTER_OUT r3 0xFFFFFFFF
+  #_ REGISTER_OUT cr 0x0000000080000000
+
+test_divdu_11:
+  #_ REGISTER_IN r0 0
+  #_ REGISTER_IN r3 0xFFFFFFFF
+  divdu. r0, r0, r3
+  blr
+  #_ REGISTER_OUT r0 0xFFFFFFFF
+  #_ REGISTER_OUT r3 0xFFFFFFFF
+  #_ REGISTER_OUT cr 0x0000000020000000

src/xenia/cpu/ppc/testing/instr_divwu.s

@@ -219,3 +219,21 @@ test_divwu_12_constant:
   #_ REGISTER_OUT r3 0
   #_ REGISTER_OUT r4 0x80000000
   #_ REGISTER_OUT r5 -1
+
+test_divwu_13:
+  #_ REGISTER_IN r0 0x1
+  #_ REGISTER_IN r3 0xFFFFFFFF
+  divwu. r0, r3, r0
+  blr
+  #_ REGISTER_OUT r0 0xFFFFFFFF
+  #_ REGISTER_OUT r3 0xFFFFFFFF
+  #_ REGISTER_OUT cr 0x0000000080000000
+
+test_divwu_14:
+  #_ REGISTER_IN r0 0x1
+  #_ REGISTER_IN r3 0xFFFFFFFF
+  divwu. r0, r0, r3
+  blr
+  #_ REGISTER_OUT r0 0
+  #_ REGISTER_OUT r3 0xFFFFFFFF
+  #_ REGISTER_OUT cr 0x0000000020000000

src/xenia/cpu/ppc/testing/instr_mulhwu.s

@@ -111,3 +111,21 @@ test_mulhwu_6_constant:
   #_ REGISTER_OUT r3 0x00000000FFFFFFFE
   #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
   #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_mulhwu_7:
+  #_ REGISTER_IN r0 0x1
+  #_ REGISTER_IN r3 0xFFFFFFFF
+  mulhwu. r0, r3, r0
+  blr
+  #_ REGISTER_OUT r0 0
+  #_ REGISTER_OUT r3 0xFFFFFFFF
+  #_ REGISTER_OUT cr 0x0000000020000000
+
+test_mulhwu_8:
+  #_ REGISTER_IN r0 0x1
+  #_ REGISTER_IN r3 0x1FFFFFFFF
+  mulhwu. r0, r3, r0
+  blr
+  #_ REGISTER_OUT r0 0
+  #_ REGISTER_OUT r3 0x1FFFFFFFF
+  #_ REGISTER_OUT cr 0x0000000020000000