[D3D12] DXT1 untiling

src/xenia/gpu/d3d12/shaders/byte_swap.hlsli

@@ -0,0 +1,19 @@
+#ifndef XENIA_GPU_D3D12_SHADERS_BYTE_SWAP_HLSLI_
+#define XENIA_GPU_D3D12_SHADERS_BYTE_SWAP_HLSLI_
+
+#define XE_BYTE_SWAP_OVERLOAD(XeByteSwapType) \
+XeByteSwapType XeByteSwap(XeByteSwapType v, uint endian) { \
+  [flatten] if (((endian ^ (endian >> 1u)) & 1u) != 0u) { \
+    v = ((v & 0x00FF00FFu) << 8u) | ((v & 0xFF00FF00u) >> 8u); \
+  } \
+  [flatten] if ((endian & 2u) != 0u) { \
+    v = (v << 16u) | (v >> 16u); \
+  } \
+  return v; \
+}
+XE_BYTE_SWAP_OVERLOAD(uint)
+XE_BYTE_SWAP_OVERLOAD(uint2)
+XE_BYTE_SWAP_OVERLOAD(uint3)
+XE_BYTE_SWAP_OVERLOAD(uint4)
+
+#endif  // XENIA_GPU_D3D12_SHADERS_BYTE_SWAP_HLSLI_

src/xenia/gpu/d3d12/shaders/texture_address.hlsli

@@ -0,0 +1,52 @@
+#ifndef XENIA_GPU_D3D12_SHADERS_TEXTURE_ADDRESS_HLSLI_
+#define XENIA_GPU_D3D12_SHADERS_TEXTURE_ADDRESS_HLSLI_
+
+// XeTiledOffset function take x/y in blocks and returns byte offsets for 4
+// consecutive blocks along X.
+
+// https://github.com/gildor2/UModel/blob/de8fbd3bc922427ea056b7340202dcdcc19ccff5/Unreal/UnTexture.cpp#L495
+uint4 XeTextureTiledOffset2D(uint2 p, uint width, uint log2_bpb) {
+  uint4 x4 = uint4(0u, 1u, 2u, 3u) + p.xxxx;
+  // Top bits of coordinates.
+  uint4 macro =
+      ((x4 >> 5u) + (p.y >> 5u) * ((width + 31u) >> 5u)) << (log2_bpb + 7u);
+  // Lower bits of coordinates (result is 6-bit value).
+  uint4 micro = ((x4 & 7u) + ((p.y & 0xEu) << 2u)) << log2_bpb;
+  // Mix micro/macro + add few remaining x/y bits.
+  uint4 offset =
+      macro + ((micro & ~0xFu) << 1u) + (micro & 0xFu) + ((p.y & 1u) << 4u);
+  // Mix bits again.
+  return ((offset & ~0x1FFu) << 3u) +  // Upper bits (offset bits [*-9]).
+         ((p.y & 16u) << 7u) +  // Next 1 bit.
+         ((offset & 0x1C0u) << 2u) +  // Next 3 bits (offset bits [8-6]).
+         ((((x4 >> 3u) + ((p.y & 8u) >> 2u)) & 3u) << 6u) +  // Next 2 bits.
+         (offset & 0x3Fu);  // Lower 6 bits (offset bits [5-0]).
+}
+
+// Reverse-engineered from an executable.
+// The base/micro/macro names were chosen pretty much at random and don't have
+// the same meaning as in TiledOffset2D.
+uint4 XeTextureTiledOffset3D(uint3 p, uint2 width_height, uint log2_bpb) {
+  uint4 x4 = uint4(0u, 1u, 2u, 3u) + p.xxxx;
+  uint2 aligned_size = (width_height + 31u) & ~31u;
+  uint base = ((p.z >> 2u) * ((aligned_size.x * aligned_size.y) >> 4u) +
+               (p.y >> 4u)) * (aligned_size.x >> 5u);
+  uint4 micro = (((p.z >> 2u) + (p.y >> 3u)) & 1u).xxxx;
+  micro += (((micro << 1u) + (x4 >> 3u)) & 3u) << 1u;
+  uint4 macro = (((x4 & 7u) + ((p.y & 6u) << 2u)) << (log2_bpb + 6u)) >> 6u;
+  macro = (((((((x4 >> 5u) + base) << (log2_bpb + 6u)) & 0xFFFFFFFu) << 1u) +
+            (macro & ~15u)) << 1u) + (macro & 15u) +
+            ((p.z & 3u) << (log2_bpb + 6u)) + ((p.y & 1u) << 4u);
+  return ((((((((macro >> 6u) & 7u) + ((micro & 1u) << 3u)) << 3u) +
+             (micro & ~1u)) << 2u) + (macro & ~511u)) << 3u) + (macro & 63u);
+}
+
+uint XeTextureGuestLinearOffset(uint3 p, uint height, uint pitch, uint bpb) {
+  return p.x * bpb + ((p.z * ((height + 31u) & ~31u) + pitch) * p.y);
+}
+
+uint XeTextureHostLinearOffset(uint3 p, uint height, uint pitch, uint bpb) {
+  return p.x * bpb + ((p.z * height + pitch) * p.y);
+}
+
+#endif  // XENIA_GPU_D3D12_SHADERS_TEXTURE_ADDRESS_HLSLI_

src/xenia/gpu/d3d12/shaders/texture_copy.hlsli

@@ -0,0 +1,28 @@
+#ifndef XENIA_GPU_D3D12_SHADERS_TEXTURE_COPY_HLSLI_
+#define XENIA_GPU_D3D12_SHADERS_TEXTURE_COPY_HLSLI_
+
+#include "byte_swap.hlsli"
+#include "texture_address.hlsli"
+
+cbuffer xe_texture_copy_constants : register(b0) {
+  uint xe_texture_copy_guest_base;
+  // For linear textures - row byte pitch.
+  uint xe_texture_copy_guest_pitch;
+  uint xe_texture_copy_host_base;
+  uint xe_texture_copy_host_pitch;
+
+  // Size in blocks.
+  uint3 xe_texture_copy_size;
+  bool xe_texture_copy_is_3d;
+
+  // Offset within the packed mip for small mips.
+  uint3 xe_texture_copy_guest_mip_offset;
+  uint xe_texture_copy_endianness;
+};
+
+#define XeTextureCopyGuestPitchTiled 0xFFFFFFFFu
+
+ByteAddressBuffer xe_texture_copy_source : register(t0);
+RWByteAddressBuffer xe_texture_copy_dest : register(u0);
+
+#endif  // XENIA_GPU_D3D12_SHADERS_TEXTURE_COPY_HLSLI_

src/xenia/gpu/d3d12/shaders/texture_load_64bpb.cs.hlsl

@@ -0,0 +1,38 @@
+#include "texture_copy.hlsli"
+
+[numthreads(8, 32, 1)]
+void main(uint3 xe_thread_id : SV_DispatchThreadID) {
+  // 1 thread = 4 uint2 blocks.
+  uint3 block_index = xe_thread_id;
+  block_index.x <<= 2u;
+  [branch] if (any(block_index >= xe_texture_copy_size)) {
+    return;
+  }
+  uint3 block_index_guest = block_index + xe_texture_copy_guest_mip_offset;
+  uint4 block_offsets_guest;
+  [branch] if (xe_texture_copy_guest_pitch == XeTextureCopyGuestPitchTiled) {
+    [branch] if (xe_texture_copy_is_3d) {
+      block_offsets_guest = XeTextureTiledOffset3D(
+          block_index_guest, xe_texture_copy_size.xy, 3u);
+    } else {
+      block_offsets_guest = XeTextureTiledOffset2D(
+          block_index_guest.xy, xe_texture_copy_size.x, 3u);
+    }
+  } else {
+    block_offsets_guest = uint4(0u, 8u, 16u, 24u) + XeTextureGuestLinearOffset(
+        block_index_guest, xe_texture_copy_size.y, xe_texture_copy_guest_pitch,
+        8u);
+  }
+  block_offsets_guest += xe_texture_copy_guest_base;
+  uint4 blocks_01 = uint4(xe_texture_copy_source.Load2(block_offsets_guest.x),
+                          xe_texture_copy_source.Load2(block_offsets_guest.y));
+  uint4 blocks_23 = uint4(xe_texture_copy_source.Load2(block_offsets_guest.z),
+                          xe_texture_copy_source.Load2(block_offsets_guest.w));
+  blocks_01 = XeByteSwap(blocks_01, xe_texture_copy_endianness);
+  blocks_23 = XeByteSwap(blocks_23, xe_texture_copy_endianness);
+  uint block_offset_host = XeTextureHostLinearOffset(
+      block_index, xe_texture_copy_size.y, xe_texture_copy_host_pitch, 8u) +
+      xe_texture_copy_host_base;
+  xe_texture_copy_dest.Store4(block_offset_host, blocks_01);
+  xe_texture_copy_dest.Store4(block_offset_host + 16u, blocks_23);
+}