Reworking translator code to be pretty sexy.
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@@ -102,6 +102,22 @@ constexpr bool IsControlFlowOpcodeExec(ControlFlowOpcode opcode) {
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opcode == ControlFlowOpcode::kCondExecPredCleanEnd;
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}
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// Returns true if the given control flow opcode terminates the shader after
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// executing.
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constexpr bool DoesControlFlowOpcodeEndShader(ControlFlowOpcode opcode) {
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return opcode == ControlFlowOpcode::kExecEnd ||
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opcode == ControlFlowOpcode::kCondExecEnd ||
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opcode == ControlFlowOpcode::kCondExecPredEnd ||
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opcode == ControlFlowOpcode::kCondExecPredCleanEnd;
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}
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// Returns true if the given control flow opcode resets the predicate prior to
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// execution.
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constexpr bool DoesControlFlowOpcodeCleanPredicate(ControlFlowOpcode opcode) {
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return opcode == ControlFlowOpcode::kCondExecPredClean ||
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opcode == ControlFlowOpcode::kCondExecPredCleanEnd;
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}
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// Determines whether addressing is based on a0 or aL.
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enum class AddressingMode : uint32_t {
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// Indexing into register sets is done based on aL.
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@@ -117,7 +133,7 @@ enum class AddressingMode : uint32_t {
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// shader.
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enum class AllocType : uint32_t {
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// ?
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kNoAlloc = 0,
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kNone = 0,
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// Vertex shader exports a position.
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kVsPosition = 1,
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// Vertex shader exports interpolators.
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@@ -791,9 +807,7 @@ struct AluInstruction {
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bool is_const_1_addressed() const { return data_.const_1_rel_abs == 1; }
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bool is_address_relative() const { return data_.address_absolute == 1; }
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bool has_vector_op() const {
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return vector_write_mask() || (is_export() && export_write_mask());
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}
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bool has_vector_op() const { return vector_write_mask() || is_export(); }
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AluVectorOpcode vector_opcode() const {
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return static_cast<AluVectorOpcode>(data_.vector_opc);
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}
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@@ -804,7 +818,7 @@ struct AluInstruction {
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bool has_scalar_op() const {
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return scalar_opcode() != AluScalarOpcode::kRETAIN_PREV ||
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scalar_write_mask() != 0;
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(!is_export() && scalar_write_mask() != 0);
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}
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AluScalarOpcode scalar_opcode() const {
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return static_cast<AluScalarOpcode>(data_.scalar_opc);
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