Now tracking register accesses for each function.

include/xenia/cpu/codegen/function_generator.h

@@ -91,7 +91,8 @@ public:
 
 private:
   void GenerateSharedBlocks();
-  void GenerateBasicBlock(sdb::FunctionBlock* block, llvm::BasicBlock* bb);
+  void PrepareBasicBlock(sdb::FunctionBlock* block);
+  void GenerateBasicBlock(sdb::FunctionBlock* block);
 
   void setup_xer();
   void setup_lr();
@@ -118,8 +119,9 @@ private:
   std::map<uint32_t, llvm::BasicBlock*> bbs_;
 
   // Address of the instruction being generated.
-  uint32_t      cia_;
+  uint32_t        cia_;
 
+  ppc::InstrAccessBits access_bits_;
   struct {
     llvm::Value*  indirection_target;
     llvm::Value*  indirection_cia;

include/xenia/cpu/ppc/instr.h

@@ -250,6 +250,25 @@ typedef struct {
 } InstrOperand;
 
 
+class InstrAccessBits {
+public:
+  InstrAccessBits() : spr(0), cr(0), gpr(0), fpr(0) {}
+
+  // Bitmasks derived from the accesses to registers.
+  // Format is 2 bits for each register, even bits indicating reads and odds
+  // indicating writes.
+  uint64_t spr;   // fpcsr/ctr/lr/xer
+  uint64_t cr;    // cr7/6/5/4/3/2/1/0
+  uint64_t gpr;   // r31-0
+  uint64_t fpr;   // f31-0
+
+  void Clear();
+  void Extend(InstrAccessBits& other);
+  void MarkAccess(InstrRegister& reg);
+  void Dump(std::string& out_str);
+};
+
+
 class InstrDisasm {
 public:
   enum Flags {
@@ -263,6 +282,7 @@ public:
   char      info[64];
   std::vector<InstrOperand> operands;
   std::vector<InstrRegister> special_registers;
+  InstrAccessBits access_bits;
 
   void Init(std::string name, std::string info, uint32_t flags);
   void AddLR(InstrRegister::Access access);
@@ -274,11 +294,6 @@ public:
   void AddUImmOperand(uint64_t value, size_t width, std::string display = "");
   int Finish();
 
-  // TODO(benvanik): fast checks
-  uint64_t reg_mask;
-  uint64_t gpr_mask;
-  uint64_t fpr_mask;
-
   void Dump(std::string& str, size_t pad = 8);
 };