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Merge branch 'master' into d3d12

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This commit is contained in:
Triang3l
2018-11-22 20:59:55 +03:00
parent 14b623465c 086d7e9da7
commit da280347c4
130 changed files with 481 additions and 248 deletions
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6
src/xenia/gpu/command_processor.cc
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@@ -347,8 +347,8 @@ void CommandProcessor::MakeCoherent() {
// some way to check for dest coherency (what all the COHER_DEST_BASE_*
// registers are for).
// Best docs I've found on this are here:
// http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/10/R6xx_R7xx_3D.pdf
// http://cgit.freedesktop.org/xorg/driver/xf86-video-radeonhd/tree/src/r6xx_accel.c?id=3f8b6eccd9dba116cc4801e7f80ce21a879c67d2#n454
// https://web.archive.org/web/20160711162346/https://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/10/R6xx_R7xx_3D.pdf
// https://cgit.freedesktop.org/xorg/driver/xf86-video-radeonhd/tree/src/r6xx_accel.c?id=3f8b6eccd9dba116cc4801e7f80ce21a879c67d2#n454
RegisterFile* regs = register_file_;
auto status_host = regs->values[XE_GPU_REG_COHER_STATUS_HOST].u32;
@@ -1392,7 +1392,7 @@ bool CommandProcessor::ExecutePacketType3_VIZ_QUERY(RingBuffer* reader,
uint32_t packet,
uint32_t count) {
// begin/end initiator for viz query extent processing
// http://www.google.com/patents/US20050195186
// https://www.google.com/patents/US20050195186
assert_true(count == 1);
uint32_t dword0 = reader->ReadAndSwap<uint32_t>();

4
src/xenia/gpu/glsl_shader_translator.cc
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@@ -131,8 +131,8 @@ struct VertexData {
};
)");
// http://www.nvidia.com/object/cube_map_ogl_tutorial.html
// http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf
// https://www.nvidia.com/object/cube_map_ogl_tutorial.html
// https://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf
// src0 = Rn.zzxy, src1 = Rn.yxzz
// dst.W = FaceId;
// dst.Z = 2.0f * MajorAxis;

6
src/xenia/gpu/graphics_system.cc
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@@ -26,8 +26,8 @@ namespace gpu {
// Nvidia Optimus/AMD PowerXpress support.
// These exports force the process to trigger the discrete GPU in multi-GPU
// systems.
// http://developer.download.nvidia.com/devzone/devcenter/gamegraphics/files/OptimusRenderingPolicies.pdf
// http://stackoverflow.com/questions/17458803/amd-equivalent-to-nvoptimusenablement
// https://developer.download.nvidia.com/devzone/devcenter/gamegraphics/files/OptimusRenderingPolicies.pdf
// https://stackoverflow.com/questions/17458803/amd-equivalent-to-nvoptimusenablement
#if XE_PLATFORM_WIN32
extern "C" {
__declspec(dllexport) uint32_t NvOptimusEnablement = 0x00000001;
@@ -74,7 +74,7 @@ X_STATUS GraphicsSystem::Setup(cpu::Processor* processor,
"Ensure you have the latest drivers for your GPU and "
"that it supports Vulkan.\n"
"\n"
"See http://xenia.jp/faq/ for more information and a list of "
"See https://xenia.jp/faq/ for more information and a list of "
"supported GPUs.");
return X_STATUS_UNSUCCESSFUL;
}

2
src/xenia/gpu/shader_translator.cc
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@@ -40,7 +40,7 @@ using namespace ucode;
// https://github.com/freedreno/freedreno/blob/master/util/disasm-a2xx.c
//
// Lots of naming comes from the disassembly spit out by the XNA GS compiler
// and dumps of d3dcompiler and games: http://pastebin.com/i4kAv7bB
// and dumps of d3dcompiler and games: https://pastebin.com/i4kAv7bB
ShaderTranslator::ShaderTranslator() = default;

2
src/xenia/gpu/texture_conversion.cc
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@@ -48,7 +48,7 @@ void CopySwapBlock(Endian endian, void* output, const void* input,
void ConvertTexelCTX1ToR8G8(Endian endian, void* output, const void* input,
size_t length) {
// http://fileadmin.cs.lth.se/cs/Personal/Michael_Doggett/talks/unc-xenos-doggett.pdf
// https://fileadmin.cs.lth.se/cs/Personal/Michael_Doggett/talks/unc-xenos-doggett.pdf
union {
uint8_t data[8];
struct {

2
src/xenia/gpu/texture_info.cc
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@@ -26,7 +26,7 @@ using namespace xe::gpu::xenos;
bool TextureInfo::Prepare(const xe_gpu_texture_fetch_t& fetch,
TextureInfo* out_info) {
// http://msdn.microsoft.com/en-us/library/windows/desktop/cc308051(v=vs.85).aspx
// https://msdn.microsoft.com/en-us/library/windows/desktop/cc308051(v=vs.85).aspx
// a2xx_sq_surfaceformat
std::memset(out_info, 0, sizeof(TextureInfo));

2
src/xenia/gpu/trace_dump.cc
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@@ -103,7 +103,7 @@ int TraceDump::Main(const std::vector<std::wstring>& args) {
bool TraceDump::Setup() {
// Create the emulator but don't initialize so we can setup the window.
emulator_ = std::make_unique<Emulator>(L"");
emulator_ = std::make_unique<Emulator>(L"", L"");
X_STATUS result = emulator_->Setup(
nullptr, nullptr, [this]() { return CreateGraphicsSystem(); }, nullptr);
if (XFAILED(result)) {

2
src/xenia/gpu/trace_viewer.cc
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@@ -122,7 +122,7 @@ bool TraceViewer::Setup() {
window_->Resize(1920, 1200);
// Create the emulator but don't initialize so we can setup the window.
emulator_ = std::make_unique<Emulator>(L"");
emulator_ = std::make_unique<Emulator>(L"", L"");
X_STATUS result =
emulator_->Setup(window_.get(), nullptr,
[this]() { return CreateGraphicsSystem(); }, nullptr);

4
src/xenia/gpu/ucode.h
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@@ -17,7 +17,7 @@
#include "xenia/gpu/xenos.h"
// Closest AMD doc:
// http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf
// https://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf
// Microcode format differs, but most fields/enums are the same.
// This code comes from the freedreno project:
@@ -701,7 +701,7 @@ static_assert_size(TextureFetchInstruction, 12);
// R600 docs that have a near 1:1 with the instructions available in the xenos
// GPU. Some of the behavior has been experimentally verified. Some has been
// guessed.
// Docs: http://www.x.org/docs/AMD/old/r600isa.pdf
// Docs: https://www.x.org/docs/AMD/old/r600isa.pdf
//
// Conventions:
// - All temporary registers are vec4s.

4
src/xenia/gpu/vulkan/pipeline_cache.cc
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@@ -660,7 +660,7 @@ bool PipelineCache::SetDynamicState(VkCommandBuffer command_buffer,
}
// Whether each of the viewport settings are enabled.
// http://www.x.org/docs/AMD/old/evergreen_3D_registers_v2.pdf
// https://www.x.org/docs/AMD/old/evergreen_3D_registers_v2.pdf
bool vport_xscale_enable = (regs.pa_cl_vte_cntl & (1 << 0)) > 0;
bool vport_xoffset_enable = (regs.pa_cl_vte_cntl & (1 << 1)) > 0;
bool vport_yscale_enable = (regs.pa_cl_vte_cntl & (1 << 2)) > 0;
@@ -865,7 +865,7 @@ bool PipelineCache::SetDynamicState(VkCommandBuffer command_buffer,
push_constants.window_scale[3] = (-1280.f / window_height_scalar) + 0.5f;
}
// http://www.x.org/docs/AMD/old/evergreen_3D_registers_v2.pdf
// https://www.x.org/docs/AMD/old/evergreen_3D_registers_v2.pdf
// VTX_XY_FMT = true: the incoming XY have already been multiplied by 1/W0.
// = false: multiply the X, Y coordinates by 1/W0.
// VTX_Z_FMT = true: the incoming Z has already been multiplied by 1/W0.

2
src/xenia/gpu/vulkan/render_cache.cc
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@@ -786,7 +786,7 @@ bool RenderCache::ParseConfiguration(RenderConfiguration* config) {
config->mode_control = regs.rb_modecontrol.edram_mode;
// RB_SURFACE_INFO
// http://fossies.org/dox/MesaLib-10.3.5/fd2__gmem_8c_source.html
// https://fossies.org/dox/MesaLib-10.3.5/fd2__gmem_8c_source.html
config->surface_pitch_px = regs.rb_surface_info.surface_pitch;
config->surface_msaa = regs.rb_surface_info.msaa_samples;

4
src/xenia/gpu/vulkan/texture_config.cc
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@@ -99,7 +99,7 @@ const TextureConfig texture_configs[64] = {
/* k_16_MPEG_INTERLACED */ ___(UNDEFINED),
/* k_16_16_MPEG_INTERLACED */ ___(UNDEFINED),
// http://fileadmin.cs.lth.se/cs/Personal/Michael_Doggett/talks/unc-xenos-doggett.pdf
// https://fileadmin.cs.lth.se/cs/Personal/Michael_Doggett/talks/unc-xenos-doggett.pdf
/* k_DXN */ ___(BC5_UNORM_BLOCK), // ?
/* k_8_8_8_8_AS_16_16_16_16 */ ___(R8G8B8A8_UNORM),
@@ -116,7 +116,7 @@ const TextureConfig texture_configs[64] = {
/* k_DXT3A */ _c_(BC2_UNORM_BLOCK, ___R),
/* k_DXT5A */ _c_(BC4_UNORM_BLOCK, RRRR), // ATI1N
// http://fileadmin.cs.lth.se/cs/Personal/Michael_Doggett/talks/unc-xenos-doggett.pdf
// https://fileadmin.cs.lth.se/cs/Personal/Michael_Doggett/talks/unc-xenos-doggett.pdf
/* k_CTX1 */ ___(R8G8_UINT),
/* k_DXT3A_AS_1_1_1_1 */ ___(UNDEFINED),

2
src/xenia/gpu/vulkan/vulkan_command_processor.cc
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@@ -916,7 +916,7 @@ bool VulkanCommandProcessor::IssueCopy() {
assert_true(copy_regs->copy_mask == 0);
// RB_SURFACE_INFO
// http://fossies.org/dox/MesaLib-10.3.5/fd2__gmem_8c_source.html
// https://fossies.org/dox/MesaLib-10.3.5/fd2__gmem_8c_source.html
uint32_t surface_info = regs[XE_GPU_REG_RB_SURFACE_INFO].u32;
uint32_t surface_pitch = surface_info & 0x3FFF;
auto surface_msaa = static_cast<MsaaSamples>((surface_info >> 16) & 0x3);

2
src/xenia/gpu/xenos.h
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@@ -68,7 +68,7 @@ enum class TextureSign : uint32_t {
kUnsigned = 0,
// Two's complement texture data.
kSigned = 1,
// 2*color-1 - http://xboxforums.create.msdn.com/forums/t/107374.aspx
// 2*color-1 - https://xboxforums.create.msdn.com/forums/t/107374.aspx
kUnsignedBiased = 2,
// Linearized when sampled.
kGamma = 3,