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[D3D12] Pass adaptive tessellation factors via index buffer like on the guest

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Triang3l
2020-04-05 17:22:49 +03:00
parent 5d6fe38e6f
commit e82d05c687
41 changed files with 2071 additions and 1911 deletions
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64
src/xenia/gpu/d3d12/shaders/dxbc/adaptive_triangle_hs.txt
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@@ -2,19 +2,15 @@
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Note: shader requires additional functionality:
// UAVs at every shader stage
//
//
// Buffer Definitions:
//
// cbuffer xe_system_cbuffer
// {
//
// uint xe_flags; // Offset: 0 Size: 4
// uint xe_flags; // Offset: 0 Size: 4 [unused]
// uint xe_line_loop_closing_index; // Offset: 4 Size: 4 [unused]
// uint xe_vertex_index_endian_and_edge_factors;// Offset: 8 Size: 4
// int xe_vertex_base_index; // Offset: 12 Size: 4
// uint xe_vertex_index_endian; // Offset: 8 Size: 4 [unused]
// int xe_vertex_base_index; // Offset: 12 Size: 4 [unused]
// float4 xe_user_clip_planes[6]; // Offset: 16 Size: 96 [unused]
// float3 xe_ndc_scale; // Offset: 112 Size: 12 [unused]
// uint xe_pixel_pos_reg; // Offset: 124 Size: 4 [unused]
@@ -49,8 +45,6 @@
//
// Name Type Format Dim ID HLSL Bind Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_shared_memory_srv texture byte r/o T0 t0 1
// xe_shared_memory_uav UAV byte r/w U0 u0 1
// xe_system_cbuffer cbuffer NA NA CB0 cb0 1
//
//
@@ -69,7 +63,8 @@
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
// XEVERTEXID 0 x 0 NONE int x
//
//
// Output signature:
//
@@ -93,44 +88,23 @@ dcl_tessellator_partitioning partitioning_fractional_even
dcl_tessellator_output_primitive output_triangle_cw
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][15], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
hs_control_point_phase
ret
hs_fork_phase
dcl_input vPrim
dcl_hs_fork_phase_instance_count 3
dcl_input vForkInstanceID
dcl_input vicp[3][0].x
dcl_output_siv o0.x, finalTriUeq0EdgeTessFactor
dcl_output_siv o1.x, finalTriVeq0EdgeTessFactor
dcl_output_siv o2.x, finalTriWeq0EdgeTessFactor
dcl_temps 3
imul null, r0.x, CB0[0][0].w, l(3)
imad r0.x, vPrim, l(3), r0.x
and r0.yzw, CB0[0][0].zzxz, l(0, 0x1ffffffc, 1, 2)
ishl r0.x, r0.x, l(2)
iadd r0.x, r0.x, r0.y
if_nz r0.z
ld_raw r1.xyz, r0.x, U0[0].xyzx
else
ld_raw r1.xyz, r0.x, T0[0].xyzx
endif
ushr r0.x, CB0[0][0].z, l(1)
xor r0.x, r0.x, CB0[0][0].z
and r0.x, r0.x, l(1)
if_nz r0.x
ishl r0.xyz, r1.xyzx, l(8, 8, 8, 0)
and r0.xyz, r0.xyzx, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0)
ushr r2.xyz, r1.xyzx, l(8, 8, 8, 0)
and r2.xyz, r2.xyzx, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0)
iadd r1.xyz, r0.xyzx, r2.xyzx
endif
if_nz r0.w
ushr r0.xyz, r1.xyzx, l(16, 16, 16, 0)
bfi r1.xyz, l(16, 16, 16, 0), l(16, 16, 16, 0), r1.xyzx, r0.xyzx
endif
add r0.xyz, r1.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
max r0.xyz, r0.xyzx, CB0[0][14].xxxx
min r0.xyz, r0.xyzx, CB0[0][14].yyyy
mov o0.x, r0.z
mov o1.x, r0.y
mov o2.x, r0.x
dcl_temps 1
dcl_indexrange o0.x 3
ineg r0.x, vForkInstanceID.x
add r0.x, l(1.000000), vicp[r0.x + 2][0].x
max r0.x, r0.x, CB0[0][14].x
min r0.x, r0.x, CB0[0][14].y
mov r0.y, vForkInstanceID.x
mov o[r0.y + 0].x, r0.x
ret
hs_join_phase
dcl_input vpc0.x
@@ -141,4 +115,4 @@ dcl_temps 1
min r0.x, vpc0.x, vpc1.x
min o3.x, r0.x, vpc2.x
ret
// Approximately 34 instruction slots used
// Approximately 11 instruction slots used