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atomic cas use prefetchw if available

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remove useless memorybarrier
remove double membarrier in wait pm4 cmd
add int64 cvar
use int64 cvar for x64 feature mask
Rework some functions that were frontend bound according to vtune placing some of their code in different noinline functions, profiling after indicating l1 cache misses decreased and perf of func increased
remove long vpinsrd dep chain code for conversion.h, instead do normal load+bswap or movbe if avail
Much faster entry table via split_map, code size could be improved though
GetResolveInfo was very large and had impact on icache, mark callees as noinline + msvc pragma optimize small
use log2 shifts instead of integer divides in memory
minor optimizations in PhysicalHeap::EnableAccessCallbacks, the majority of time in the function is spent looping, NOT calling Protect! Someone should optimize this function and rework the algo completely
remove wonky scheduling log message, it was spammy and unhelpful
lock count was unnecessary for criticalsection mutex, criticalsection is already a recursive mutex
brief notes i gotta run
This commit is contained in:
chss95cs@gmail.com
2022-09-17 04:04:53 -07:00
parent 0fd4a2533b
commit eb8154908c
35 changed files with 942 additions and 738 deletions
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39
src/xenia/apu/conversion.h
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@@ -20,6 +20,8 @@ namespace apu {
namespace conversion {
#if XE_ARCH_AMD64
#if 0
inline void sequential_6_BE_to_interleaved_6_LE(float* output,
const float* input,
size_t ch_sample_count) {
@@ -41,7 +43,44 @@ inline void sequential_6_BE_to_interleaved_6_LE(float* output,
out[sample * 6 + 5] = sample2;
}
}
#else
XE_NOINLINE
static void _generic_sequential_6_BE_to_interleaved_6_LE(
float* XE_RESTRICT output, const float* XE_RESTRICT input,
unsigned ch_sample_count) {
for (unsigned sample = 0; sample < ch_sample_count; sample++) {
for (unsigned channel = 0; channel < 6; channel++) {
unsigned int value = *reinterpret_cast<const unsigned int*>(
&input[channel * ch_sample_count + sample]);
*reinterpret_cast<unsigned int*>(&output[sample * 6 + channel]) =
xe::byte_swap(value);
}
}
}
XE_NOINLINE
static void _movbe_sequential_6_BE_to_interleaved_6_LE(
float* XE_RESTRICT output, const float* XE_RESTRICT input,
unsigned ch_sample_count) {
for (unsigned sample = 0; sample < ch_sample_count; sample++) {
for (unsigned channel = 0; channel < 6; channel++) {
*reinterpret_cast<unsigned int*>(&output[sample * 6 + channel]) =
_load_be_u32(reinterpret_cast<const unsigned int*>(
&input[channel * ch_sample_count + sample]));
}
}
}
inline static void sequential_6_BE_to_interleaved_6_LE(
float* output, const float* input, unsigned ch_sample_count) {
if (amd64::GetFeatureFlags() & amd64::kX64EmitMovbe) {
_movbe_sequential_6_BE_to_interleaved_6_LE(output, input, ch_sample_count);
} else {
_generic_sequential_6_BE_to_interleaved_6_LE(output, input,
ch_sample_count);
}
}
#endif
inline void sequential_6_BE_to_interleaved_2_LE(float* output,
const float* input,
size_t ch_sample_count) {