atomic cas use prefetchw if available
remove useless memorybarrier remove double membarrier in wait pm4 cmd add int64 cvar use int64 cvar for x64 feature mask Rework some functions that were frontend bound according to vtune placing some of their code in different noinline functions, profiling after indicating l1 cache misses decreased and perf of func increased remove long vpinsrd dep chain code for conversion.h, instead do normal load+bswap or movbe if avail Much faster entry table via split_map, code size could be improved though GetResolveInfo was very large and had impact on icache, mark callees as noinline + msvc pragma optimize small use log2 shifts instead of integer divides in memory minor optimizations in PhysicalHeap::EnableAccessCallbacks, the majority of time in the function is spent looping, NOT calling Protect! Someone should optimize this function and rework the algo completely remove wonky scheduling log message, it was spammy and unhelpful lock count was unnecessary for criticalsection mutex, criticalsection is already a recursive mutex brief notes i gotta run
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@@ -334,7 +334,7 @@ void CommandProcessor::EnableReadPointerWriteBack(uint32_t ptr,
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void CommandProcessor::UpdateWritePointer(uint32_t value) {
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write_ptr_index_ = value;
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write_ptr_index_event_->Set();
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write_ptr_index_event_->SetBoostPriority();
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}
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void CommandProcessor::HandleSpecialRegisterWrite(uint32_t index,
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uint32_t value) {
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@@ -665,6 +665,11 @@ uint32_t CommandProcessor::ExecutePrimaryBuffer(uint32_t read_index,
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reader_.set_read_offset(read_index * sizeof(uint32_t));
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reader_.set_write_offset(write_index * sizeof(uint32_t));
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// prefetch the wraparound range
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// it likely is already in L3 cache, but in a zen system it may be another
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// chiplets l3
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reader_.BeginPrefetchedRead<swcache::PrefetchTag::Level2>(
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GetCurrentRingReadCount());
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do {
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if (!ExecutePacket()) {
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// This probably should be fatal - but we're going to continue anyways.
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