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load_acquire/store_release

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This commit is contained in:
Ben Vanik
2013-12-08 14:15:28 -08:00
parent 2549292a57
commit ec4bf50363
4 changed files with 147 additions and 3 deletions
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142
src/alloy/backend/ivm/ivm_intcode.cc
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@@ -1246,6 +1246,61 @@ int Translate_LOAD(TranslationContext& ctx, Instr* i) {
return DispatchToC(ctx, i, fns[i->dest->type]);
}
uint32_t IntCode_LOAD_ACQUIRE_I8(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
xe_atomic_exchange_32(address, ics.reserve_address);
ics.rf[i->dest_reg].i8 = *((int8_t*)(ics.membase + address));
return IA_NEXT;
}
uint32_t IntCode_LOAD_ACQUIRE_I16(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
xe_atomic_exchange_32(address, ics.reserve_address);
ics.rf[i->dest_reg].i16 = *((int16_t*)(ics.membase + address));
return IA_NEXT;
}
uint32_t IntCode_LOAD_ACQUIRE_I32(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
xe_atomic_exchange_32(address, ics.reserve_address);
ics.rf[i->dest_reg].i32 = *((int32_t*)(ics.membase + address));
return IA_NEXT;
}
uint32_t IntCode_LOAD_ACQUIRE_I64(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
xe_atomic_exchange_32(address, ics.reserve_address);
ics.rf[i->dest_reg].i64 = *((int64_t*)(ics.membase + address));
return IA_NEXT;
}
uint32_t IntCode_LOAD_ACQUIRE_F32(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
xe_atomic_exchange_32(address, ics.reserve_address);
ics.rf[i->dest_reg].f32 = *((float*)(ics.membase + address));
return IA_NEXT;
}
uint32_t IntCode_LOAD_ACQUIRE_F64(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
xe_atomic_exchange_32(address, ics.reserve_address);
ics.rf[i->dest_reg].f64 = *((double*)(ics.membase + address));
return IA_NEXT;
}
uint32_t IntCode_LOAD_ACQUIRE_V128(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
xe_atomic_exchange_32(address, ics.reserve_address);
ics.rf[i->dest_reg].v128 = *((vec128_t*)(ics.membase + (address & ~0xF)));
return IA_NEXT;
}
int Translate_LOAD_ACQUIRE(TranslationContext& ctx, Instr* i) {
static IntCodeFn fns[] = {
IntCode_LOAD_ACQUIRE_I8,
IntCode_LOAD_ACQUIRE_I16,
IntCode_LOAD_ACQUIRE_I32,
IntCode_LOAD_ACQUIRE_I64,
IntCode_LOAD_ACQUIRE_F32,
IntCode_LOAD_ACQUIRE_F64,
IntCode_LOAD_ACQUIRE_V128,
};
return DispatchToC(ctx, i, fns[i->dest->type]);
}
uint32_t IntCode_STORE_I8(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
if (DYNAMIC_REGISTER_ACCESS_CHECK(address)) {
@@ -1331,6 +1386,89 @@ int Translate_STORE(TranslationContext& ctx, Instr* i) {
return DispatchToC(ctx, i, fns[i->src2.value->type]);
}
uint32_t IntCode_STORE_RELEASE_I8(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
int8_t stored = 0;
if (xe_atomic_exchange_32(0, ics.reserve_address) == address) {
*((int8_t*)(ics.membase + address)) = ics.rf[i->src2_reg].i8;
stored = 1;
}
ics.rf[i->dest_reg].i8 = stored;
return IA_NEXT;
}
uint32_t IntCode_STORE_RELEASE_I16(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
int8_t stored = 0;
if (xe_atomic_exchange_32(0, ics.reserve_address) == address) {
*((int16_t*)(ics.membase + address)) = ics.rf[i->src2_reg].i16;
stored = 1;
}
ics.rf[i->dest_reg].i8 = stored;
return IA_NEXT;
}
uint32_t IntCode_STORE_RELEASE_I32(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
int8_t stored = 0;
if (xe_atomic_exchange_32(0, ics.reserve_address) == address) {
*((int32_t*)(ics.membase + address)) = ics.rf[i->src2_reg].i32;
stored = 1;
}
ics.rf[i->dest_reg].i8 = stored;
return IA_NEXT;
}
uint32_t IntCode_STORE_RELEASE_I64(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
int8_t stored = 0;
if (xe_atomic_exchange_32(0, ics.reserve_address) == address) {
*((int64_t*)(ics.membase + address)) = ics.rf[i->src2_reg].i64;
stored = 1;
}
ics.rf[i->dest_reg].i8 = stored;
return IA_NEXT;
}
uint32_t IntCode_STORE_RELEASE_F32(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
int8_t stored = 0;
if (xe_atomic_exchange_32(0, ics.reserve_address) == address) {
*((float*)(ics.membase + address)) = ics.rf[i->src2_reg].f32;
stored = 1;
}
ics.rf[i->dest_reg].i8 = stored;
return IA_NEXT;
}
uint32_t IntCode_STORE_RELEASE_F64(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
int8_t stored = 0;
if (xe_atomic_exchange_32(0, ics.reserve_address) == address) {
*((double*)(ics.membase + address)) = ics.rf[i->src2_reg].f64;
stored = 1;
}
ics.rf[i->dest_reg].i8 = stored;
return IA_NEXT;
}
uint32_t IntCode_STORE_RELEASE_V128(IntCodeState& ics, const IntCode* i) {
uint32_t address = ics.rf[i->src1_reg].u32;
int8_t stored = 0;
if (xe_atomic_exchange_32(0, ics.reserve_address) == address) {
*((vec128_t*)(ics.membase + (address & ~0xF))) = ics.rf[i->src2_reg].v128;
stored = 1;
}
ics.rf[i->dest_reg].i8 = stored;
return IA_NEXT;
}
int Translate_STORE_RELEASE(TranslationContext& ctx, Instr* i) {
static IntCodeFn fns[] = {
IntCode_STORE_RELEASE_I8,
IntCode_STORE_RELEASE_I16,
IntCode_STORE_RELEASE_I32,
IntCode_STORE_RELEASE_I64,
IntCode_STORE_RELEASE_F32,
IntCode_STORE_RELEASE_F64,
IntCode_STORE_RELEASE_V128,
};
return DispatchToC(ctx, i, fns[i->src2.value->type]);
}
uint32_t IntCode_PREFETCH(IntCodeState& ics, const IntCode* i) {
return IA_NEXT;
}
@@ -2865,9 +3003,9 @@ static const TranslateFn dispatch_table[] = {
Translate_STORE_CONTEXT,
Translate_LOAD,
TranslateInvalid, //Translate_LOAD_ACQUIRE,
Translate_LOAD_ACQUIRE,
Translate_STORE,
TranslateInvalid, //Translate_STORE_RELEASE,
Translate_STORE_RELEASE,
Translate_PREFETCH,
TranslateInvalid, //Translate_MAX,