From ef505fbe3dcb145bf8e5a870b2f78d0524eea746 Mon Sep 17 00:00:00 2001
From: "Herman S." <429230+has207@users.noreply.github.com>
Date: Sun, 28 Dec 2025 14:47:26 +0900
Subject: [PATCH] [Vulkan] add no_discard_stencil_in_transfer_pipelines support

---
 src/xenia/gpu/d3d12/d3d12_render_target_cache.cc   | 1 -
 src/xenia/gpu/gpu_flags.cc                         | 5 +++++
 src/xenia/gpu/gpu_flags.h                          | 2 ++
 src/xenia/gpu/vulkan/vulkan_render_target_cache.cc | 3 ++-
 4 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/xenia/gpu/d3d12/d3d12_render_target_cache.cc b/src/xenia/gpu/d3d12/d3d12_render_target_cache.cc
index 36eda1585..ffc5ee24c 100644
--- a/src/xenia/gpu/d3d12/d3d12_render_target_cache.cc
+++ b/src/xenia/gpu/d3d12/d3d12_render_target_cache.cc
@@ -37,7 +37,6 @@ DEFINE_bool(
     "Allow stencil reference output usage on Direct3D 12 on Intel GPUs - not "
     "working on UHD Graphics 630 as of March 2021 (driver 27.20.0100.8336).",
     "GPU");
-DEFINE_bool(no_discard_stencil_in_transfer_pipelines, false, "bleh", "GPU");
 // TODO(Triang3l): Make ROV the default when it's optimized better (for
 // instance, using static shader modifications to pass render target
 // parameters).
diff --git a/src/xenia/gpu/gpu_flags.cc b/src/xenia/gpu/gpu_flags.cc
index 0859842af..5ab1af8ed 100644
--- a/src/xenia/gpu/gpu_flags.cc
+++ b/src/xenia/gpu/gpu_flags.cc
@@ -84,3 +84,8 @@ DEFINE_int32(anisotropic_override, -1,
              "  4 = Force 8x anisotropic filtering\n"
              "  5 = Force 16x anisotropic filtering",
              "GPU");
+
+DEFINE_bool(no_discard_stencil_in_transfer_pipelines, false,
+            "Skip stencil bit discard in render target transfer pipelines. "
+            "May improve performance on some GPUs.",
+            "GPU");
diff --git a/src/xenia/gpu/gpu_flags.h b/src/xenia/gpu/gpu_flags.h
index a85e66e62..bfeefdc53 100644
--- a/src/xenia/gpu/gpu_flags.h
+++ b/src/xenia/gpu/gpu_flags.h
@@ -34,6 +34,8 @@ DECLARE_int32(anisotropic_override);
 
 DECLARE_bool(disassemble_pm4);
 
+DECLARE_bool(no_discard_stencil_in_transfer_pipelines);
+
 #define XE_GPU_FINE_GRAINED_DRAW_SCOPES 1
 
 #endif  // XENIA_GPU_GPU_FLAGS_H_
diff --git a/src/xenia/gpu/vulkan/vulkan_render_target_cache.cc b/src/xenia/gpu/vulkan/vulkan_render_target_cache.cc
index 97fd8d3c4..923135029 100644
--- a/src/xenia/gpu/vulkan/vulkan_render_target_cache.cc
+++ b/src/xenia/gpu/vulkan/vulkan_render_target_cache.cc
@@ -19,6 +19,7 @@
 #include "xenia/base/logging.h"
 #include "xenia/base/math.h"
 #include "xenia/gpu/draw_util.h"
+#include "xenia/gpu/gpu_flags.h"
 #include "xenia/gpu/registers.h"
 #include "xenia/gpu/spirv_builder.h"
 #include "xenia/gpu/spirv_compatibility.h"
@@ -4281,7 +4282,7 @@ VkShaderModule VulkanRenderTargetCache::GetTransferShader(
         }
       } break;
       case TransferOutput::kStencilBit: {
-        if (packed) {
+        if (packed && !cvars::no_discard_stencil_in_transfer_pipelines) {
           // Kill the sample if the needed stencil bit is not set.
           assert_true(push_constants_member_stencil_mask != UINT32_MAX);
           id_vector_temp.clear();