fabi/Xenia-Canary
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

XECOUNT to countof.

Browse Source
This commit is contained in:
Ben Vanik
2014-08-16 17:58:33 -07:00
parent 187d0ad277
commit f2a9fa3bf9
30 changed files with 195 additions and 175 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/alloy/backend/x64/x64_sequences.cc
View File

@@ -1017,7 +1017,7 @@ EMITTER(LOAD_VECTOR_SHL_I8, MATCH(I<OPCODE_LOAD_VECTOR_SHL, V128<>, I8<>>)) {
static void Emit(X64Emitter& e, const EmitArgType& i) {
if (i.src1.is_constant) {
auto sh = i.src1.constant();
assert_true(sh < XECOUNT(lvsl_table));
assert_true(sh < poly::countof(lvsl_table));
e.mov(e.rax, (uintptr_t)&lvsl_table[sh]);
e.vmovaps(i.dest, e.ptr[e.rax]);
} else {
@@ -1069,7 +1069,7 @@ EMITTER(LOAD_VECTOR_SHR_I8, MATCH(I<OPCODE_LOAD_VECTOR_SHR, V128<>, I8<>>)) {
static void Emit(X64Emitter& e, const EmitArgType& i) {
if (i.src1.is_constant) {
auto sh = i.src1.constant();
assert_true(sh < XECOUNT(lvsr_table));
assert_true(sh < poly::countof(lvsr_table));
e.mov(e.rax, (uintptr_t)&lvsr_table[sh]);
e.vmovaps(i.dest, e.ptr[e.rax]);
} else {

8
src/alloy/compiler/passes/register_allocation_pass.cc
View File

@@ -55,7 +55,7 @@ RegisterAllocationPass::RegisterAllocationPass(const MachineInfo* machine_info)
}
RegisterAllocationPass::~RegisterAllocationPass() {
for (size_t n = 0; n < XECOUNT(usage_sets_.all_sets); n++) {
for (size_t n = 0; n < poly::countof(usage_sets_.all_sets); n++) {
if (!usage_sets_.all_sets[n]) {
break;
}
@@ -171,7 +171,7 @@ int RegisterAllocationPass::Run(HIRBuilder* builder) {
void RegisterAllocationPass::DumpUsage(const char* name) {
#if 0
fprintf(stdout, "\n%s:\n", name);
for (size_t i = 0; i < XECOUNT(usage_sets_.all_sets); ++i) {
for (size_t i = 0; i < poly::countof(usage_sets_.all_sets); ++i) {
auto usage_set = usage_sets_.all_sets[i];
if (usage_set) {
fprintf(stdout, "set %s:\n", usage_set->set->name);
@@ -190,7 +190,7 @@ void RegisterAllocationPass::DumpUsage(const char* name) {
}
void RegisterAllocationPass::PrepareBlockState() {
for (size_t i = 0; i < XECOUNT(usage_sets_.all_sets); ++i) {
for (size_t i = 0; i < poly::countof(usage_sets_.all_sets); ++i) {
auto usage_set = usage_sets_.all_sets[i];
if (usage_set) {
usage_set->availability.set();
@@ -201,7 +201,7 @@ void RegisterAllocationPass::PrepareBlockState() {
}
void RegisterAllocationPass::AdvanceUses(Instr* instr) {
for (size_t i = 0; i < XECOUNT(usage_sets_.all_sets); ++i) {
for (size_t i = 0; i < poly::countof(usage_sets_.all_sets); ++i) {
auto usage_set = usage_sets_.all_sets[i];
if (!usage_set) {
break;

6
src/alloy/frontend/ppc/ppc_disasm.cc
View File

@@ -294,7 +294,7 @@ void Disasm_bcx(InstrData& i, StringBuffer* str) {
}
char s2[8] = {0};
if (!select_bits(i.B.BO, 4, 4)) {
xesnprintfa(s2, XECOUNT(s2), "cr%d, ", i.B.BI >> 2);
xesnprintfa(s2, poly::countof(s2), "cr%d, ", i.B.BI >> 2);
}
uint32_t nia;
if (i.B.AA) {
@@ -310,7 +310,7 @@ void Disasm_bcctrx(InstrData& i, StringBuffer* str) {
const char* s0 = i.XL.LK ? "lr, " : "";
char s2[8] = {0};
if (!select_bits(i.XL.BO, 4, 4)) {
xesnprintfa(s2, XECOUNT(s2), "cr%d, ", i.XL.BI >> 2);
xesnprintfa(s2, poly::countof(s2), "cr%d, ", i.XL.BI >> 2);
}
str->Append("%-8s %s%sctr", i.type->name, s0, s2);
// TODO(benvanik): resolve target name?
@@ -328,7 +328,7 @@ void Disasm_bclrx(InstrData& i, StringBuffer* str) {
}
char s2[8] = {0};
if (!select_bits(i.XL.BO, 4, 4)) {
xesnprintfa(s2, XECOUNT(s2), "cr%d, ", i.XL.BI >> 2);
xesnprintfa(s2, poly::countof(s2), "cr%d, ", i.XL.BI >> 2);
}
str->Append("%-8s %s%s", name, s1, s2);
}

3
src/alloy/frontend/ppc/ppc_hir_builder.cc
View File

@@ -168,7 +168,8 @@ int PPCHIRBuilder::Emit(FunctionInfo* symbol_info, uint32_t flags) {
void PPCHIRBuilder::AnnotateLabel(uint64_t address, Label* label) {
char name_buffer[13];
xesnprintfa(name_buffer, XECOUNT(name_buffer), "loc_%.8X", (uint32_t)address);
xesnprintfa(name_buffer, poly::countof(name_buffer), "loc_%.8X",
(uint32_t)address);
label->name = (char*)arena_->Alloc(sizeof(name_buffer));
xe_copy_struct(label->name, name_buffer, sizeof(name_buffer));
}

4
src/alloy/frontend/ppc/ppc_instr.cc
View File

@@ -25,7 +25,7 @@ void InstrOperand::Dump(std::string& out_str) {
}
char buffer[32];
const size_t max_count = XECOUNT(buffer);
const size_t max_count = poly::countof(buffer);
switch (type) {
case InstrOperand::kRegister:
switch (reg.set) {
@@ -373,7 +373,7 @@ InstrType* GetInstrType(uint32_t code) {
// Slow lookup via linear scan.
// This is primarily due to laziness. It could be made fast like the others.
for (size_t n = 0;
n < XECOUNT(alloy::frontend::ppc::tables::instr_table_scan); n++) {
n < poly::countof(alloy::frontend::ppc::tables::instr_table_scan); n++) {
slot = &(alloy::frontend::ppc::tables::instr_table_scan[n]);
if (slot->opcode == (code & slot->opcode_mask)) {
return slot;

27
src/alloy/frontend/ppc/ppc_instr_tables.h
View File

@@ -13,6 +13,7 @@
#include <cmath>
#include <alloy/frontend/ppc/ppc_instr.h>
#include <poly/poly.h>
namespace alloy {
namespace frontend {
@@ -91,8 +92,8 @@ void Disasm_vspltisw(InstrData& i, StringBuffer* str);
namespace tables {
static InstrType** instr_table_prep(InstrType* unprep, int unprep_count, int a,
int b) {
static InstrType** instr_table_prep(InstrType* unprep, size_t unprep_count,
int a, int b) {
int prep_count = (int)pow(2.0, b - a + 1);
InstrType** prep = (InstrType**)xe_calloc(prep_count * sizeof(void*));
for (int n = 0; n < unprep_count; n++) {
@@ -102,7 +103,7 @@ static InstrType** instr_table_prep(InstrType* unprep, int unprep_count, int a,
return prep;
}
static InstrType** instr_table_prep_63(InstrType* unprep, int unprep_count,
static InstrType** instr_table_prep_63(InstrType* unprep, size_t unprep_count,
int a, int b) {
// Special handling for A format instructions.
int prep_count = (int)pow(2.0, b - a + 1);
@@ -362,7 +363,7 @@ static InstrType instr_table_4_unprep[] = {
"Vector Logical XOR"),
};
static InstrType** instr_table_4 = instr_table_prep(
instr_table_4_unprep, XECOUNT(instr_table_4_unprep), 0, 11);
instr_table_4_unprep, poly::countof(instr_table_4_unprep), 0, 11);
// Opcode = 19, index = bits 10-1 (10)
static InstrType instr_table_19_unprep[] = {
@@ -382,7 +383,7 @@ static InstrType instr_table_19_unprep[] = {
"Branch Conditional to Count Register"),
};
static InstrType** instr_table_19 = instr_table_prep(
instr_table_19_unprep, XECOUNT(instr_table_19_unprep), 1, 10);
instr_table_19_unprep, poly::countof(instr_table_19_unprep), 1, 10);
// Opcode = 30, index = bits 4-1 (4)
static InstrType instr_table_30_unprep[] = {
@@ -398,7 +399,7 @@ static InstrType instr_table_30_unprep[] = {
// INSTRUCTION(rldcrx, 0x78000012, MDS, General , 0),
};
static InstrType** instr_table_30 = instr_table_prep(
instr_table_30_unprep, XECOUNT(instr_table_30_unprep), 0, 0);
instr_table_30_unprep, poly::countof(instr_table_30_unprep), 0, 0);
// Opcode = 31, index = bits 10-1 (10)
static InstrType instr_table_31_unprep[] = {
@@ -645,7 +646,7 @@ static InstrType instr_table_31_unprep[] = {
"Store Vector Right Indexed LRU"),
};
static InstrType** instr_table_31 = instr_table_prep(
instr_table_31_unprep, XECOUNT(instr_table_31_unprep), 1, 10);
instr_table_31_unprep, poly::countof(instr_table_31_unprep), 1, 10);
// Opcode = 58, index = bits 1-0 (2)
static InstrType instr_table_58_unprep[] = {
@@ -656,7 +657,7 @@ static InstrType instr_table_58_unprep[] = {
"Load Word Algebraic"),
};
static InstrType** instr_table_58 = instr_table_prep(
instr_table_58_unprep, XECOUNT(instr_table_58_unprep), 0, 1);
instr_table_58_unprep, poly::countof(instr_table_58_unprep), 0, 1);
// Opcode = 59, index = bits 5-1 (5)
static InstrType instr_table_59_unprep[] = {
@@ -682,7 +683,7 @@ static InstrType instr_table_59_unprep[] = {
"Floating Negative Multiply-Add [Single]"),
};
static InstrType** instr_table_59 = instr_table_prep(
instr_table_59_unprep, XECOUNT(instr_table_59_unprep), 1, 5);
instr_table_59_unprep, poly::countof(instr_table_59_unprep), 1, 5);
// Opcode = 62, index = bits 1-0 (2)
static InstrType instr_table_62_unprep[] = {
@@ -691,7 +692,7 @@ static InstrType instr_table_62_unprep[] = {
"Store Doubleword with Update"),
};
static InstrType** instr_table_62 = instr_table_prep(
instr_table_62_unprep, XECOUNT(instr_table_62_unprep), 0, 1);
instr_table_62_unprep, poly::countof(instr_table_62_unprep), 0, 1);
// Opcode = 63, index = bits 10-1 (10)
// NOTE: the A format instructions need some special handling because
@@ -751,7 +752,7 @@ static InstrType instr_table_63_unprep[] = {
"Floating Convert From Integer Doubleword"),
};
static InstrType** instr_table_63 = instr_table_prep_63(
instr_table_63_unprep, XECOUNT(instr_table_63_unprep), 1, 10);
instr_table_63_unprep, poly::countof(instr_table_63_unprep), 1, 10);
// Main table, index = bits 31-26 (6) : (code >> 26)
static InstrType instr_table_unprep[64] = {
@@ -830,8 +831,8 @@ static InstrType instr_table_unprep[64] = {
INSTRUCTION(stfdu, 0xDC000000, D, General, D_FRT_RA_I,
"Store Floating-Point Double with Update"),
};
static InstrType** instr_table =
instr_table_prep(instr_table_unprep, XECOUNT(instr_table_unprep), 26, 31);
static InstrType** instr_table = instr_table_prep(
instr_table_unprep, poly::countof(instr_table_unprep), 26, 31);
// Altivec instructions.
// TODO(benvanik): build a table like the other instructions.