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[GPU] Cleanup: XEPACKED -> static_assert_size/alignas

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This commit is contained in:
Triang3l
2021-05-16 14:03:36 +03:00
parent 165c6f0e4d
commit f39020700a
4 changed files with 187 additions and 130 deletions
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95
src/xenia/gpu/ucode.h
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@@ -45,6 +45,10 @@
* SOFTWARE.
*/
// Only 32-bit types (uint32_t, int32_t or enums with uint32_t / int32_t as the
// underlying type) are allowed in the bit fields here, as Visual C++ restarts
// packing when a field requires different alignment than the previous one.
namespace xe {
namespace gpu {
namespace ucode {
@@ -175,7 +179,7 @@ struct ControlFlowExecInstruction {
AddressingMode address_mode_ : 1;
ControlFlowOpcode opcode_ : 4;
};
static_assert_size(ControlFlowExecInstruction, 8);
static_assert_size(ControlFlowExecInstruction, sizeof(uint32_t) * 2);
// Instruction data for ControlFlowOpcode::kCondExec and kCondExecEnd.
struct ControlFlowCondExecInstruction {
@@ -209,7 +213,7 @@ struct ControlFlowCondExecInstruction {
AddressingMode address_mode_ : 1;
ControlFlowOpcode opcode_ : 4;
};
static_assert_size(ControlFlowCondExecInstruction, 8);
static_assert_size(ControlFlowCondExecInstruction, sizeof(uint32_t) * 2);
// Instruction data for ControlFlowOpcode::kCondExecPred, kCondExecPredEnd,
// kCondExecPredClean, kCondExecPredCleanEnd.
@@ -245,7 +249,7 @@ struct ControlFlowCondExecPredInstruction {
AddressingMode address_mode_ : 1;
ControlFlowOpcode opcode_ : 4;
};
static_assert_size(ControlFlowCondExecPredInstruction, 8);
static_assert_size(ControlFlowCondExecPredInstruction, sizeof(uint32_t) * 2);
// Instruction data for ControlFlowOpcode::kLoopStart.
struct ControlFlowLoopStartInstruction {
@@ -272,7 +276,7 @@ struct ControlFlowLoopStartInstruction {
AddressingMode address_mode_ : 1;
ControlFlowOpcode opcode_ : 4;
};
static_assert_size(ControlFlowLoopStartInstruction, 8);
static_assert_size(ControlFlowLoopStartInstruction, sizeof(uint32_t) * 2);
// Instruction data for ControlFlowOpcode::kLoopEnd.
struct ControlFlowLoopEndInstruction {
@@ -302,7 +306,7 @@ struct ControlFlowLoopEndInstruction {
AddressingMode address_mode_ : 1;
ControlFlowOpcode opcode_ : 4;
};
static_assert_size(ControlFlowLoopEndInstruction, 8);
static_assert_size(ControlFlowLoopEndInstruction, sizeof(uint32_t) * 2);
// Instruction data for ControlFlowOpcode::kCondCall.
struct ControlFlowCondCallInstruction {
@@ -333,7 +337,7 @@ struct ControlFlowCondCallInstruction {
AddressingMode address_mode_ : 1;
ControlFlowOpcode opcode_ : 4;
};
static_assert_size(ControlFlowCondCallInstruction, 8);
static_assert_size(ControlFlowCondCallInstruction, sizeof(uint32_t) * 2);
// Instruction data for ControlFlowOpcode::kReturn.
struct ControlFlowReturnInstruction {
@@ -349,7 +353,7 @@ struct ControlFlowReturnInstruction {
AddressingMode address_mode_ : 1;
ControlFlowOpcode opcode_ : 4;
};
static_assert_size(ControlFlowReturnInstruction, 8);
static_assert_size(ControlFlowReturnInstruction, sizeof(uint32_t) * 2);
// Instruction data for ControlFlowOpcode::kCondJmp.
struct ControlFlowCondJmpInstruction {
@@ -381,7 +385,7 @@ struct ControlFlowCondJmpInstruction {
AddressingMode address_mode_ : 1;
ControlFlowOpcode opcode_ : 4;
};
static_assert_size(ControlFlowCondJmpInstruction, 8);
static_assert_size(ControlFlowCondJmpInstruction, sizeof(uint32_t) * 2);
// Instruction data for ControlFlowOpcode::kAlloc.
struct ControlFlowAllocInstruction {
@@ -403,9 +407,9 @@ struct ControlFlowAllocInstruction {
uint32_t : 1;
ControlFlowOpcode opcode_ : 4;
};
static_assert_size(ControlFlowAllocInstruction, 8);
static_assert_size(ControlFlowAllocInstruction, sizeof(uint32_t) * 2);
XEPACKEDUNION(ControlFlowInstruction, {
union ControlFlowInstruction {
ControlFlowOpcode opcode() const { return opcode_value; }
ControlFlowExecInstruction exec; // kExec*
@@ -418,17 +422,17 @@ XEPACKEDUNION(ControlFlowInstruction, {
ControlFlowCondJmpInstruction cond_jmp; // kCondJmp
ControlFlowAllocInstruction alloc; // kAlloc
XEPACKEDSTRUCTANONYMOUS({
struct {
uint32_t unused_0 : 32;
uint32_t unused_1 : 12;
ControlFlowOpcode opcode_value : 4;
});
XEPACKEDSTRUCTANONYMOUS({
};
struct {
uint32_t dword_0;
uint32_t dword_1;
});
});
static_assert_size(ControlFlowInstruction, 8);
};
};
static_assert_size(ControlFlowInstruction, sizeof(uint32_t) * 2);
inline void UnpackControlFlowInstructions(const uint32_t* dwords,
ControlFlowInstruction* out_ab) {
@@ -587,7 +591,7 @@ enum class FetchOpcode : uint32_t {
kSetTextureGradientsVert = 26,
};
struct VertexFetchInstruction {
struct alignas(uint32_t) VertexFetchInstruction {
FetchOpcode opcode() const { return data_.opcode_value; }
// Whether the jump is predicated (or conditional).
@@ -653,8 +657,8 @@ struct VertexFetchInstruction {
}
private:
XEPACKEDSTRUCT(Data, {
XEPACKEDSTRUCTANONYMOUS({
struct Data {
struct {
FetchOpcode opcode_value : 5;
uint32_t src_reg : 6;
uint32_t src_reg_am : 1;
@@ -666,8 +670,8 @@ struct VertexFetchInstruction {
// Prefetch count minus 1.
uint32_t prefetch_count : 3;
uint32_t src_swiz : 2;
});
XEPACKEDSTRUCTANONYMOUS({
};
struct {
uint32_t dst_swiz : 12;
uint32_t fomat_comp_all : 1;
uint32_t num_format_all : 1;
@@ -678,17 +682,18 @@ struct VertexFetchInstruction {
int32_t exp_adjust : 6;
uint32_t is_mini_fetch : 1;
uint32_t is_predicated : 1;
});
XEPACKEDSTRUCTANONYMOUS({
};
struct {
uint32_t stride : 8;
int32_t offset : 23;
uint32_t pred_condition : 1;
});
});
};
};
Data data_;
};
static_assert_size(VertexFetchInstruction, sizeof(uint32_t) * 3);
struct TextureFetchInstruction {
struct alignas(uint32_t) TextureFetchInstruction {
FetchOpcode opcode() const { return data_.opcode_value; }
// Whether the jump is predicated (or conditional).
@@ -747,8 +752,8 @@ struct TextureFetchInstruction {
float offset_z() const { return data_.offset_z * 0.5f; }
private:
XEPACKEDSTRUCT(Data, {
XEPACKEDSTRUCTANONYMOUS({
struct Data {
struct {
FetchOpcode opcode_value : 5;
uint32_t src_reg : 6;
uint32_t src_reg_am : 1;
@@ -758,8 +763,8 @@ struct TextureFetchInstruction {
uint32_t const_index : 5;
uint32_t tx_coord_denorm : 1;
uint32_t src_swiz : 6; // xyz
});
XEPACKEDSTRUCTANONYMOUS({
};
struct {
uint32_t dst_swiz : 12; // xyzw
xenos::TextureFilter mag_filter : 2;
xenos::TextureFilter min_filter : 2;
@@ -772,8 +777,8 @@ struct TextureFetchInstruction {
uint32_t use_reg_lod : 1;
uint32_t unk : 1;
uint32_t is_predicated : 1;
});
XEPACKEDSTRUCTANONYMOUS({
};
struct {
uint32_t use_reg_gradients : 1;
xenos::SampleLocation sample_location : 1;
int32_t lod_bias : 7;
@@ -783,11 +788,11 @@ struct TextureFetchInstruction {
int32_t offset_y : 5;
int32_t offset_z : 5;
uint32_t pred_condition : 1;
});
});
};
};
Data data_;
};
static_assert_size(TextureFetchInstruction, 12);
static_assert_size(TextureFetchInstruction, sizeof(uint32_t) * 3);
// What follows is largely a mash up of the microcode assembly naming and the
// R600 docs that have a near 1:1 with the instructions available in the xenos
@@ -1645,7 +1650,7 @@ enum class ExportRegister : uint32_t {
kExportData4,
};
struct AluInstruction {
struct alignas(uint32_t) AluInstruction {
// Raw accessors.
// Whether data is being exported (or written to local registers).
@@ -1762,8 +1767,8 @@ struct AluInstruction {
}
private:
XEPACKEDSTRUCT(Data, {
XEPACKEDSTRUCTANONYMOUS({
struct Data {
struct {
// If exporting, both vector and scalar operations use the vector
// destination (which can't be relative in this case).
// Not very important note: If both scalar and vector operations exporting
@@ -1789,8 +1794,8 @@ struct AluInstruction {
uint32_t vector_clamp : 1;
uint32_t scalar_clamp : 1;
AluScalarOpcode scalar_opc : 6;
});
XEPACKEDSTRUCTANONYMOUS({
};
struct {
uint32_t src3_swiz : 8;
uint32_t src2_swiz : 8;
uint32_t src1_swiz : 8;
@@ -1802,8 +1807,8 @@ struct AluInstruction {
uint32_t address_absolute : 1;
uint32_t const_1_rel_abs : 1;
uint32_t const_0_rel_abs : 1;
});
XEPACKEDSTRUCTANONYMOUS({
};
struct {
uint32_t src3_reg : 8;
uint32_t src2_reg : 8;
uint32_t src1_reg : 8;
@@ -1811,11 +1816,11 @@ struct AluInstruction {
uint32_t src3_sel : 1;
uint32_t src2_sel : 1;
uint32_t src1_sel : 1;
});
});
};
};
Data data_;
};
static_assert_size(AluInstruction, 12);
static_assert_size(AluInstruction, sizeof(uint32_t) * 3);
} // namespace ucode
} // namespace gpu