[Testing] add missing integer and rotation tests
This commit is contained in:
Herman S.
53
src/xenia/cpu/ppc/testing/instr_vcmpbfp.s
Normal file
53
src/xenia/cpu/ppc/testing/instr_vcmpbfp.s
Normal file
@@ -0,0 +1,53 @@
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test_vcmpbfp_1:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
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vcmpbfp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vcmpbfp_2:
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#_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
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vcmpbfp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vcmpbfp_3:
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#_ REGISTER_IN v3 [40400000, 40400000, 40400000, 40400000]
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#_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
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vcmpbfp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [40400000, 40400000, 40400000, 40400000]
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#_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_OUT v5 [80000000, 80000000, 80000000, 80000000]
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test_vcmpbfp_4:
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#_ REGISTER_IN v3 [C0400000, C0400000, C0400000, C0400000]
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#_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
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vcmpbfp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [C0400000, C0400000, C0400000, C0400000]
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#_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_OUT v5 [40000000, 40000000, 40000000, 40000000]
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test_vcmpbfp_5:
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#_ REGISTER_IN v3 [3F800000, C0000000, 40400000, 00000000]
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#_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
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vcmpbfp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [3F800000, C0000000, 40400000, 00000000]
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#_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_OUT v5 [00000000, 00000000, 80000000, 00000000]
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test_vcmpbfp_6:
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#_ REGISTER_IN v3 [BF800000, BF800000, BF800000, BF800000]
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#_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
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vcmpbfp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [BF800000, BF800000, BF800000, BF800000]
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#_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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53
src/xenia/cpu/ppc/testing/instr_vcmpeqfp.s
Normal file
53
src/xenia/cpu/ppc/testing/instr_vcmpeqfp.s
Normal file
@@ -0,0 +1,53 @@
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test_vcmpeqfp_1:
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#_ REGISTER_IN v3 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000]
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vcmpeqfp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpeqfp_2:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vcmpeqfp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpeqfp_3:
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#_ REGISTER_IN v3 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40A00000]
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vcmpeqfp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40A00000]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, 00000000]
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test_vcmpeqfp_4:
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#_ REGISTER_IN v3 [BF800000, C0000000, C0400000, C0800000]
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#_ REGISTER_IN v4 [BF800000, C0000000, C0400000, C0800000]
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vcmpeqfp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [BF800000, C0000000, C0400000, C0800000]
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#_ REGISTER_OUT v4 [BF800000, C0000000, C0400000, C0800000]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpeqfp_5:
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#_ REGISTER_IN v3 [3F800000, BF800000, 40000000, C0000000]
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#_ REGISTER_IN v4 [3F800001, BF800001, 40000001, C0000001]
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vcmpeqfp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [3F800000, BF800000, 40000000, C0000000]
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#_ REGISTER_OUT v4 [3F800001, BF800001, 40000001, C0000001]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vcmpeqfp_6:
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#_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vcmpeqfp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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53
src/xenia/cpu/ppc/testing/instr_vcmpequb.s
Normal file
53
src/xenia/cpu/ppc/testing/instr_vcmpequb.s
Normal file
@@ -0,0 +1,53 @@
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test_vcmpequb_1:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vcmpequb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpequb_2:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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vcmpequb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpequb_3:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
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vcmpequb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vcmpequb_4:
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#_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_IN v4 [12345678, 9ABCDEF0, 11223344, 55667788]
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vcmpequb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_OUT v4 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpequb_5:
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#_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_IN v4 [12345679, 9ABCDEF0, 11223344, 55667788]
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vcmpequb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_OUT v4 [12345679, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_OUT v5 [FFFFFF00, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpequb_6:
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#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
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#_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
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vcmpequb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
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#_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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53
src/xenia/cpu/ppc/testing/instr_vcmpequh.s
Normal file
53
src/xenia/cpu/ppc/testing/instr_vcmpequh.s
Normal file
@@ -0,0 +1,53 @@
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test_vcmpequh_1:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vcmpequh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpequh_2:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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vcmpequh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpequh_3:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
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vcmpequh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vcmpequh_4:
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#_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_IN v4 [12345678, 9ABCDEF0, 11223344, 55667788]
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vcmpequh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_OUT v4 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpequh_5:
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#_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_IN v4 [12345679, 9ABCDEF0, 11223344, 55667788]
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vcmpequh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_OUT v4 [12345679, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_OUT v5 [FFFF0000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpequh_6:
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#_ REGISTER_IN v3 [00010002, 00030004, 00050006, 00070008]
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#_ REGISTER_IN v4 [00010002, 00030004, 00050006, 00070008]
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vcmpequh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00010002, 00030004, 00050006, 00070008]
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#_ REGISTER_OUT v4 [00010002, 00030004, 00050006, 00070008]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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53
src/xenia/cpu/ppc/testing/instr_vcmpequw.s
Normal file
53
src/xenia/cpu/ppc/testing/instr_vcmpequw.s
Normal file
@@ -0,0 +1,53 @@
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test_vcmpequw_1:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vcmpequw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpequw_2:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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vcmpequw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpequw_3:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
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vcmpequw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vcmpequw_4:
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#_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_IN v4 [12345678, 9ABCDEF0, 11223344, 55667788]
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vcmpequw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_OUT v4 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpequw_5:
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#_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_IN v4 [12345678, 9ABCDEF0, 11223344, 55667789]
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vcmpequw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
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#_ REGISTER_OUT v4 [12345678, 9ABCDEF0, 11223344, 55667789]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, 00000000]
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test_vcmpequw_6:
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#_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
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#_ REGISTER_IN v4 [00000001, 00000002, 00000003, 00000004]
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vcmpequw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
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#_ REGISTER_OUT v4 [00000001, 00000002, 00000003, 00000004]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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62
src/xenia/cpu/ppc/testing/instr_vcmpgefp.s
Normal file
62
src/xenia/cpu/ppc/testing/instr_vcmpgefp.s
Normal file
@@ -0,0 +1,62 @@
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test_vcmpgefp_1:
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#_ REGISTER_IN v3 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
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vcmpgefp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpgefp_2:
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#_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
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vcmpgefp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpgefp_3:
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#_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
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vcmpgefp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000]
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#_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vcmpgefp_4:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000]
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vcmpgefp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vcmpgefp_5:
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#_ REGISTER_IN v3 [C0000000, C0000000, C0000000, C0000000]
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#_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000]
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vcmpgefp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000]
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#_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vcmpgefp_6:
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#_ REGISTER_IN v3 [3F800000, 40000000, 40400000, 40800000]
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#_ REGISTER_IN v4 [3F800000, 3F800000, 40400000, 40A00000]
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vcmpgefp v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [3F800000, 40000000, 40400000, 40800000]
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||||
#_ REGISTER_OUT v4 [3F800000, 3F800000, 40400000, 40A00000]
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||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, 00000000]
|
||||
|
||||
test_vcmpgefp_7:
|
||||
#_ REGISTER_IN v3 [80000000, 00000000, 00000000, 80000000]
|
||||
#_ REGISTER_IN v4 [00000000, 80000000, 00000000, 80000000]
|
||||
vcmpgefp v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [80000000, 00000000, 00000000, 80000000]
|
||||
#_ REGISTER_OUT v4 [00000000, 80000000, 00000000, 80000000]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
62
src/xenia/cpu/ppc/testing/instr_vcmpgtfp.s
Normal file
62
src/xenia/cpu/ppc/testing/instr_vcmpgtfp.s
Normal file
@@ -0,0 +1,62 @@
|
||||
test_vcmpgtfp_1:
|
||||
#_ REGISTER_IN v3 [40000000, 40000000, 40000000, 40000000]
|
||||
#_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
|
||||
vcmpgtfp v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000]
|
||||
#_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtfp_2:
|
||||
#_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000]
|
||||
#_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
|
||||
vcmpgtfp v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000]
|
||||
#_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtfp_3:
|
||||
#_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000]
|
||||
#_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
|
||||
vcmpgtfp v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000]
|
||||
#_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtfp_4:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000]
|
||||
vcmpgtfp v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtfp_5:
|
||||
#_ REGISTER_IN v3 [C0000000, C0000000, C0000000, C0000000]
|
||||
#_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000]
|
||||
vcmpgtfp v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000]
|
||||
#_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtfp_6:
|
||||
#_ REGISTER_IN v3 [3F800000, 40000000, 40400000, 40800000]
|
||||
#_ REGISTER_IN v4 [3F800000, 3F800000, 40400000, 40A00000]
|
||||
vcmpgtfp v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [3F800000, 40000000, 40400000, 40800000]
|
||||
#_ REGISTER_OUT v4 [3F800000, 3F800000, 40400000, 40A00000]
|
||||
#_ REGISTER_OUT v5 [00000000, FFFFFFFF, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtfp_7:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 80000000, 80000000]
|
||||
#_ REGISTER_IN v4 [00000000, 80000000, 00000000, 80000000]
|
||||
vcmpgtfp v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 80000000, 80000000]
|
||||
#_ REGISTER_OUT v4 [00000000, 80000000, 00000000, 80000000]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
62
src/xenia/cpu/ppc/testing/instr_vcmpgtsb.s
Normal file
62
src/xenia/cpu/ppc/testing/instr_vcmpgtsb.s
Normal file
@@ -0,0 +1,62 @@
|
||||
test_vcmpgtsb_1:
|
||||
#_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vcmpgtsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtsb_2:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vcmpgtsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtsb_3:
|
||||
#_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vcmpgtsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtsb_4:
|
||||
#_ REGISTER_IN v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
|
||||
#_ REGISTER_IN v4 [7E7E7E7E, 7E7E7E7E, 7E7E7E7E, 7E7E7E7E]
|
||||
vcmpgtsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
|
||||
#_ REGISTER_OUT v4 [7E7E7E7E, 7E7E7E7E, 7E7E7E7E, 7E7E7E7E]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtsb_5:
|
||||
#_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
|
||||
#_ REGISTER_IN v4 [81818181, 81818181, 81818181, 81818181]
|
||||
vcmpgtsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
|
||||
#_ REGISTER_OUT v4 [81818181, 81818181, 81818181, 81818181]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtsb_6:
|
||||
#_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vcmpgtsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtsb_7:
|
||||
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vcmpgtsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v5 [00FFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
53
src/xenia/cpu/ppc/testing/instr_vcmpgtsh.s
Normal file
53
src/xenia/cpu/ppc/testing/instr_vcmpgtsh.s
Normal file
@@ -0,0 +1,53 @@
|
||||
test_vcmpgtsh_1:
|
||||
#_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vcmpgtsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtsh_2:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vcmpgtsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtsh_3:
|
||||
#_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vcmpgtsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtsh_4:
|
||||
#_ REGISTER_IN v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
|
||||
#_ REGISTER_IN v4 [7FFE7FFE, 7FFE7FFE, 7FFE7FFE, 7FFE7FFE]
|
||||
vcmpgtsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
|
||||
#_ REGISTER_OUT v4 [7FFE7FFE, 7FFE7FFE, 7FFE7FFE, 7FFE7FFE]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtsh_5:
|
||||
#_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
|
||||
#_ REGISTER_IN v4 [80018001, 80018001, 80018001, 80018001]
|
||||
vcmpgtsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
|
||||
#_ REGISTER_OUT v4 [80018001, 80018001, 80018001, 80018001]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtsh_6:
|
||||
#_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vcmpgtsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
53
src/xenia/cpu/ppc/testing/instr_vcmpgtsw.s
Normal file
53
src/xenia/cpu/ppc/testing/instr_vcmpgtsw.s
Normal file
@@ -0,0 +1,53 @@
|
||||
test_vcmpgtsw_1:
|
||||
#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vcmpgtsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtsw_2:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vcmpgtsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtsw_3:
|
||||
#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vcmpgtsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtsw_4:
|
||||
#_ REGISTER_IN v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
|
||||
#_ REGISTER_IN v4 [7FFFFFFE, 7FFFFFFE, 7FFFFFFE, 7FFFFFFE]
|
||||
vcmpgtsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
|
||||
#_ REGISTER_OUT v4 [7FFFFFFE, 7FFFFFFE, 7FFFFFFE, 7FFFFFFE]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtsw_5:
|
||||
#_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
|
||||
#_ REGISTER_IN v4 [80000001, 80000001, 80000001, 80000001]
|
||||
vcmpgtsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
||||
#_ REGISTER_OUT v4 [80000001, 80000001, 80000001, 80000001]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtsw_6:
|
||||
#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vcmpgtsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
53
src/xenia/cpu/ppc/testing/instr_vcmpgtub.s
Normal file
53
src/xenia/cpu/ppc/testing/instr_vcmpgtub.s
Normal file
@@ -0,0 +1,53 @@
|
||||
test_vcmpgtub_1:
|
||||
#_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vcmpgtub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtub_2:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vcmpgtub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtub_3:
|
||||
#_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vcmpgtub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtub_4:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
||||
vcmpgtub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtub_5:
|
||||
#_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
|
||||
#_ REGISTER_IN v4 [81818181, 81818181, 81818181, 81818181]
|
||||
vcmpgtub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
|
||||
#_ REGISTER_OUT v4 [81818181, 81818181, 81818181, 81818181]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtub_6:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vcmpgtub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
53
src/xenia/cpu/ppc/testing/instr_vcmpgtuh.s
Normal file
53
src/xenia/cpu/ppc/testing/instr_vcmpgtuh.s
Normal file
@@ -0,0 +1,53 @@
|
||||
test_vcmpgtuh_1:
|
||||
#_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vcmpgtuh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtuh_2:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vcmpgtuh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtuh_3:
|
||||
#_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vcmpgtuh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtuh_4:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
|
||||
vcmpgtuh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtuh_5:
|
||||
#_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
|
||||
#_ REGISTER_IN v4 [80018001, 80018001, 80018001, 80018001]
|
||||
vcmpgtuh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
|
||||
#_ REGISTER_OUT v4 [80018001, 80018001, 80018001, 80018001]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtuh_6:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vcmpgtuh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
62
src/xenia/cpu/ppc/testing/instr_vcmpgtuw.s
Normal file
62
src/xenia/cpu/ppc/testing/instr_vcmpgtuw.s
Normal file
@@ -0,0 +1,62 @@
|
||||
test_vcmpgtuw_1:
|
||||
#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vcmpgtuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtuw_2:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vcmpgtuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtuw_3:
|
||||
#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vcmpgtuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtuw_4:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
|
||||
vcmpgtuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtuw_5:
|
||||
#_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
|
||||
#_ REGISTER_IN v4 [80000001, 80000001, 80000001, 80000001]
|
||||
vcmpgtuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
||||
#_ REGISTER_OUT v4 [80000001, 80000001, 80000001, 80000001]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vcmpgtuw_6:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vcmpgtuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vcmpgtuw_7:
|
||||
#_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
|
||||
#_ REGISTER_IN v4 [12345677, 9ABCDEF0, 11223344, 55667788]
|
||||
vcmpgtuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
|
||||
#_ REGISTER_OUT v4 [12345677, 9ABCDEF0, 11223344, 55667788]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, 00000000, 00000000, 00000000]
|
||||
63
src/xenia/cpu/ppc/testing/instr_vrlb.s
Normal file
63
src/xenia/cpu/ppc/testing/instr_vrlb.s
Normal file
@@ -0,0 +1,63 @@
|
||||
test_vrlb_1:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vrlb v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vrlb_2:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vrlb v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
|
||||
test_vrlb_3:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707]
|
||||
vrlb v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]
|
||||
|
||||
test_vrlb_4:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808]
|
||||
vrlb v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808]
|
||||
|
||||
test_vrlb_5:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [09090909, 09090909, 09090909, 09090909]
|
||||
vrlb v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [09090909, 09090909, 09090909, 09090909]
|
||||
|
||||
test_vrlb_6:
|
||||
#_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vrlb v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
|
||||
test_vrlb_7:
|
||||
#_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vrlb v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
|
||||
test_vrlb_8:
|
||||
#_ REGISTER_IN v3 [C3C3C3C3, C3C3C3C3, C3C3C3C3, C3C3C3C3]
|
||||
#_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
|
||||
vrlb v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [3C3C3C3C, 3C3C3C3C, 3C3C3C3C, 3C3C3C3C]
|
||||
#_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
|
||||
@@ -1,4 +1,60 @@
|
||||
test_vrlh_1:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vrlh v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vrlh_2:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vrlh v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
|
||||
test_vrlh_3:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [000F000F, 000F000F, 000F000F, 000F000F]
|
||||
vrlh v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [000F000F, 000F000F, 000F000F, 000F000F]
|
||||
|
||||
test_vrlh_4:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00100010, 00100010, 00100010, 00100010]
|
||||
vrlh v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00100010, 00100010, 00100010, 00100010]
|
||||
|
||||
test_vrlh_5:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00110011, 00110011, 00110011, 00110011]
|
||||
vrlh v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00110011, 00110011, 00110011, 00110011]
|
||||
|
||||
test_vrlh_6:
|
||||
#_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vrlh v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
|
||||
test_vrlh_7:
|
||||
#_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vrlh v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00020002, 00020002, 00020002, 00020002]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
|
||||
test_vrlh_8:
|
||||
#_ REGISTER_IN v3 [12345678, 87654321, 11223344, 55667788]
|
||||
#_ REGISTER_IN v4 [000D000D, 000D000D, 000D000D, 000D000D]
|
||||
vrlh v5, v3, v4
|
||||
@@ -6,3 +62,11 @@ test_vrlh_1:
|
||||
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
|
||||
#_ REGISTER_OUT v4 [000D000D, 000D000D, 000D000D, 000D000D]
|
||||
#_ REGISTER_OUT v5 [82460ACF, B0EC2864, 42248668, CAAC0EF1]
|
||||
|
||||
test_vrlh_9:
|
||||
#_ REGISTER_IN v3 [C003C003, C003C003, C003C003, C003C003]
|
||||
#_ REGISTER_IN v4 [00040004, 00040004, 00040004, 00040004]
|
||||
vrlh v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [003C003C, 003C003C, 003C003C, 003C003C]
|
||||
#_ REGISTER_OUT v4 [00040004, 00040004, 00040004, 00040004]
|
||||
|
||||
71
src/xenia/cpu/ppc/testing/instr_vrlw.s
Normal file
71
src/xenia/cpu/ppc/testing/instr_vrlw.s
Normal file
@@ -0,0 +1,71 @@
|
||||
test_vrlw_1:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
|
||||
vrlw v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vrlw_2:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vrlw v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
|
||||
test_vrlw_3:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [0000001F, 0000001F, 0000001F, 0000001F]
|
||||
vrlw v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [0000001F, 0000001F, 0000001F, 0000001F]
|
||||
|
||||
test_vrlw_4:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000020, 00000020, 00000020, 00000020]
|
||||
vrlw v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000020, 00000020, 00000020, 00000020]
|
||||
|
||||
test_vrlw_5:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000021, 00000021, 00000021, 00000021]
|
||||
vrlw v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000021, 00000021, 00000021, 00000021]
|
||||
|
||||
test_vrlw_6:
|
||||
#_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vrlw v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
|
||||
test_vrlw_7:
|
||||
#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vrlw v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000002, 00000002, 00000002, 00000002]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
|
||||
test_vrlw_8:
|
||||
#_ REGISTER_IN v3 [12345678, 87654321, ABCDEF01, FEDCBA98]
|
||||
#_ REGISTER_IN v4 [00000008, 00000010, 00000004, 0000000C]
|
||||
vrlw v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [34567812, 43218765, BCDEF01A, CBA98FED]
|
||||
#_ REGISTER_OUT v4 [00000008, 00000010, 00000004, 0000000C]
|
||||
|
||||
test_vrlw_9:
|
||||
#_ REGISTER_IN v3 [C0000003, C0000003, C0000003, C0000003]
|
||||
#_ REGISTER_IN v4 [00000004, 00000004, 00000004, 00000004]
|
||||
vrlw v3, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [0000003C, 0000003C, 0000003C, 0000003C]
|
||||
#_ REGISTER_OUT v4 [00000004, 00000004, 00000004, 00000004]
|
||||
Reference in New Issue
Block a user